F84045 Asiliant Technologies, F84045 Datasheet - Page 148

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Rotating priority is used for selecting the VL master when more than one is requesting. The order is LREQ0#,
LREQ1#, LREQ2#. The DMA controller has a higher priority than any VL master.
LREQ0# and LGNT0# have dedicated pins.
LREQ1# and LGNT1# share pins with the SLOW# and FLUSH# pins respectively. Register 0Bh bit 3 selects the
function of these pins. The power-up default is SLOW# and FLUSH#, with Index 08h = '00h,' as well. The result is
that the state of the SLOW# input has no effect, and the FLUSH# output is driven high. Performance control (Index
08h) is the only source for FLUSH# in the SIPC. If the FLUSH# pin is actually being used as LGNT1#, there is no
conflict since the SIPC will be driving it high.
LREQ2# and LGNT2# share pins with SA17 and SA18 respectively. The functions of these pins must be set at reset
time or the system may not boot up correctly, since proper SA17 function may be needed by the BIOS ROM. On the
other hand, systems that use LREQ2# and LGNT2# would have several problems if these signals were driven with
address bits. These pins must operate in their proper functions at power-up. To accomplish this, the DGNT# pin is
sampled and internally latched at the end of SYSRESET to select the function. This pin is normally an output but is
floated from when PWRGOOD is low until SYSRESET goes low. Putting a pull-down on DGNT# selects LREQ2#
and LGNT2# (along with the IOCS# input on SA19) while putting a pull-up on DGNT# selects SA17:19.
Arbitration for more than one set of LREQ# / LGNT# signals adds 1 clock of overhead for synchronization for master
switching. If only LREQ0# and LGNT0# are needed and sets 1 and 2 are disabled, this extra clock is eliminated,
resulting in a slight arbitration performance advantage.
6.5.3. Main Arbitration Logic
The primary function of the arbitration logic is to arbitrate the system bus between the CPU, VL masters, and the DMA
controller (which is also used by ISA masters to get the bus). There are several other functions it must perform,
generally to prevent certain things from happening at the same time.
By default the CPU has the bus. The CPU is put in HOLD when any other master needs the bus. There is a two way
arbitration between Local Bus Masters and the DMA controller The CPU might not get control of the bus between a
local master access and a DMA cycle. The arbitration is performed using SCLK, and all signals are synchronous to it.
The DMA controller HOLD is synchronized to SCLK before being used by the arbitration logic.
There is a fixed priority to bus activity. The priority is as follows:
Note that either a local master or the CPU have control of the bus when a hidden refresh occurs. Hidden refresh is
listed above because it may not occur when the DMA controller has the bus, and it has a lower priority. For instance, if
the DMA controller requests the bus and a hidden refresh request occurs before the CPU or local master gives up the
bus, the hidden refresh will be delayed until after the DMA controller gives up the bus.
A DMA request will preempt a VL master using the standard VL bus protocol.
Revision 1.0
1. DMA controller
2. Hidden Refresh
3. Local Master
4. CPU
2/10/95
Subject to change without notice
147
Preliminary
Functional Description
CS4041