F84045 Asiliant Technologies, F84045 Datasheet - Page 97

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The following table lists when line fills occur for each setting of the code/data configuration bits. Line fills only occur
on memory reads to cacheable areas.
The code/data configuration bits may be changed on the fly without affecting cache coherency. These bits do not affect
caching in the L1 (CPU) cache. Best system performance normally should result from caching both instructions and
data.
5.9.5. Write Protection
Shadow RAM may be write protected, which causes a problem in the 486 cache. It is not possible to write protect the
486 cache. Several situations which occur in ATs require shadowed BIOSes to be write protected, such as:
1.
2.
3.
Items 1 and 2 pose a problem with the 486 cache. #3 is not a problem since the CPU is not doing the writing (an
invalidate will occur to the 486 cache). There are several solutions, with various degrees of success and performance.
On CPUs with a write back cache Solution C causes a problem if the BIOS is cached in write back mode. The writes
will never be seen on the bus, so the EADS# will not be generated. To get around this, the WB / WT# pin (a
multifunction pin) goes to the write through mode for write protected areas during cache line fills.
5.9.5.1. Changing a DRAM Write Protect Bit
Changing a DRAM area from write enabled to write disabled can be a problem for an L1 writeback cache. There is no
problem with L2 cache (WB or WT) or with L1 cache if it is write-through. Index 18h bit 6 can be set to ‘1’ to force all
writes to shadow RAM to be write-thrrough in L1 cache.
Revision 1.0
Some programs search for ROMs by writing a location and reading it back to see if the data changed. Write
protection properly simulates a ROM in this case.
Some adapter boards (very few) have write only registers memory mapped in the BIOS areas.
Some programs do a floppy disk verify (checking the CRC) by aiming the DMA address at the ROM. If it's
not write protected, it is overwritten.
Solution A: Don't write protect the BIOS.
Solution B: Cache only in secondary cache. Still burst to the 486.
Solution C: Drive EADS# on writes to write protected areas:
Disadvantages: Not a 100% solution. A write/read combination could occur before the EADS#. In
2/10/95
Index 22h Config Bits
00
01
10
Advantages:
Disadvantages: Does NOT handle the 3 problems above.
4041 CHIPSet
Advantages:
Disadvantages: BIOS runs slower.
4041 CHIPSet
Advantage:
practice this has not been a problem.
4041 CHIPSet
Subject to change without notice
Instruction Cache
Highest performance.
Supported. Will not write protect in DRAM or either cache.
It works 100%.
Not Supported.
High performance (almost as fast as Solution A).
Supported. Recommended solution.
Cache Type
Data Cache
Unified
96
Line fills occur when:
All memory reads
D/C# = 0
D/C# = 1
Preliminary
Functional Description
CS4041