F84045 Asiliant Technologies, F84045 Datasheet - Page 79

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.4. Arbitration
The arbitration logic is contained in the SIPC. The 4041 chip receives the CPU HLDA, DGNT#, and MASTER# to
determine what device is in control of the bus. The encoding is as follows:
The major functions controlled by the arbitration signals are as follows:
5.5. Address Mapping
5.5.1. I/O Addressing
All I/O accesses go to the ISA bus except:
There are several fixed and several programmable I/O decodes.
The fixed decodes are for internal I/O including the IPC, configuration registers, and the fast IDE controller (when
enabled).
Revision 1.0
The 4041 chip does not generate parity for CPU writes to DRAM, but does for local masters, DMA and ISA
The control link functions change (particularly the SIPC to 4041 direction) with DGNT#.
When DGNT# is high, the 4041 chip is a local bus slave and the ISA bus master. ISA bus cycles are generated
When DGNT# is low, the 4041 chip is the local bus master and an ISA bus slave. Local bus cycles are
When DGNT# is low and HLDA is high and MASTER# is high, the 4041 chip drives A10-16 with the
VL-Bus claimed I/O accesses (LDEV# low)
Table 5.3: Bus Owner Indication
masters (HLDA used to select).
in response to local bus activity.
generated in response to ISA bus activity. CPU writeback cycles cause the 4041 to become a slave on
the CPU side, while holding the DMA controller or ISA Master in wait states.
contents of the DMA latch.
Fast IDE controller I/O accesses (various addresses).
2/10/95
CPU Writeback during ISA Master access
CPU Writeback during DMA cycle
Local Bus Master
DMA controller
ISA Bus Master
Bus Owner
(Invalid)
(Invalid)
CPU
Subject to change without notice
78
HLDA
0
0
0
0
1
1
1
1
DGNT#
0
0
1
1
0
0
1
1
MASTER
Preliminary
Functional Description
0
1
0
1
0
1
0
1
#
CS4041