F84045 Asiliant Technologies, F84045 Datasheet - Page 157

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The Timer 0 value results in IRQ1 occurring approximately 18 times per second, which is used by DOS for a time-of-
day clock (separate from the 32.768 KHz based RTC, but initialized by DOS based on the hardware RTC).
The Speaker signal is inverted before being driven out on the SPKR pin (see Port 61h description).
6.9.4. RTC
The IPC contains the equivalent of a Motorola 146818 RTC/CMOS RAM chip. An extra 64 bytes of CMOS RAM
have been added and are normally used to store chipset specific information. The RTC is accessed through an address
register at port 70h, and a data port at address 71h. Bit 7 of port 70h is the NMI mask, and should be written to a 0,
which enables the NMI.
The interrupt output of the RTC goes to IR0 of the slave controller, which is IRQ8. This may be programmed to
provide a periodic interrupt, or an alarm interrupt. It is normally disabled.
The RTC runs off of a 32.768KHz crystal. It is powered by a small battery when the system power is off (the entire
4045 is powered up but is in very low ICC standby mode when PWRGOOD is low).
External RTC. The internal RTC can be disabled, if desired, to allow an external RTC to be used instead. Index 0Ah
bit 7, when set to ‘1’, disables the 4045 internal RTC. I/O address decoding for ports 70h/71h (except 70h bit 7)
requires a few gates of external logic when the internal RTC is disabled. GPC or GPD from the 4041 may be useful as
I/O decodes for an external RTC. Port 70h bit 7 (NMI disable) is implemented in the 4041 and remains under 4041
control as usual. The function of the 32KX1 pin changes to become the IRQ8# input for the external RTC interrupt.
IRQ8# is active-low (unlike other IRQ inputs), allowing the INT# output of most typical external RTCs to connect
directly to the 4045 IRQ8# pin without an external inverter. The 32 KHz oscillator for the external RTC becomes the
responsibility of external logic. All CMOS RAM information needed by the system (normally 64 bytes minimum) also
becomes the responsibility of external logic when the internal RTC is disabled.
Special care may be needed to maintain the lowest possible standby current in an external RTC when main system
power is turned off. The most popular external RTC devices may have provision, such as an on-chip VCC detector, for
achieving low standby power without requiring special support logic. When using an older device such as an
MC146818, however, the CE# pin on the external RTC normally should be connected to PWRGOOD through an
inverter (such as an MC14069) that is also connected to battery power. It is particularly important not to gate CE# with
any devices or signals (such as IOR# or IOW# or any other 4041 signals) that do not remain powered when main
Revision 1.0
14.3MHz
Port 61 bit 0
Port 61 bit 1
A0
A1
IOR#
IOW#
2/10/95
Div 12
Figure 6.5 8254 Timer Internal Connections
1.19MHz
Subject to change without notice
CS# 40:43
+5
+5
Within IPC Megacell
GATE0
CLK0
GATE1
CLK1
GATE2
CLK2
A0
A1
CS
RD
WR
8254
156
OUT0
OUT1
OUT2
D0
D1
D2
D3
D4
D5
D6
D7
(Periodic Interrupt)
XD0:7
IRQ0
Refresh Request
Port 61 bit 5
Preliminary
Functional Description
Speaker
CS4041