F84045 Asiliant Technologies, F84045 Datasheet - Page 151

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Subject to change without notice
Functional Description
6.6. Performance Control (DeTurbo)
“DeTurbo” or Performance control refers to slowing down the system to approximately that of an 8MHz IBM AT to
allow some old software, which cannot operate on a fast machine, to be used. This is becoming less and less of an
issue as this software becomes increasingly out of date and infrequently used.
In the past, this was often accomplished by switching the clock to about 8MHz. With the advent of SL Enhanced
CPUs and Green PCs we are again switching the clock, but this time for power savings. The performance control logic
in the 4035 and 4045 puts the CPU in hold for a programmable percentage of time instead of switching the clock,
leaving clock control entirely to the power management software.
Performance reduction via HOLD is implemented based on refresh. On every refresh request, the CPU is put in HOLD
for a programmable period of time. Optionally, the FLUSH# pin is also pulled low during this time to make sure the
CPU doesn't continue to execute out of its internal cache. The length of the HOLD pulse is selected to provide the
desired degradation in performance. The intent is to match the speed of a 6 or 8 MHz AT in order to allow some games
and copy protection programs to work properly. The FLUSH# and HOLD functions may be enabled separately, but
generally they will be used together.
After the HOLD duration is set (Index 08h), the slow mode may be enabled and disabled by either of two ways: Index
register access or the SLOW# input signal. This is an OR function, allowing either of them to slow the system down
(they both should be disabled for full speed).
The clock generated for the IPC DMA controllers is used for the time base of the performance control. This clock is
normally about 8 MHz (0.125
s period). The corresponding maximum HOLD delay programmable via Index 08h is
15.9 s (127 cycles of 0.125 s). However, to avoid possible system lockup, care must be taken not to program a delay
greater than the time between refresh cycles, normally about 15
s (18 cycles of 1.193 MHz). With a 486 CPU running
at 25 MHz or more, Index 08h probably will need to set in the range of F0h to F8h (close to the refresh period) to
reduce effective system performance to the 6 to 8 MHz range.
The HOLD is initiated each time the refresh request occurs from timer 1. Local bus master, DMA, ISA master, or
refresh cycles may occur while the performance control HOLD is taking place, avoiding a DMA underrun or overrun.
Note that the FLUSH# pin on the CPU is also optionally driven by the 4041. If both the performance control and
power management FLUSH# functions are required, a low-true OR function (physical AND gate) must be used
externally. The 4041 is designed such that the FLUSH# pin is not required for SMM mode in most cases, so only the
4045 FLUSH# signal need be used.
6.7. Refresh
The SIPC performs the ISA bus refresh. It drives SA0:7, REFRESH#, and MEMR# directly.
When timer 1 produces a refresh request, it sets a " RefreshPending" flip-flop. The output of this flip-flop is then
arbitrated with the internal HLDA for the DMA controllers. Internal HLDA for DMA will not go active when the
hidden refresh sequence is taking place, and the hidden refresh sequence will not begin while internal HLDA for DMA
is high.
When hidden refresh wins the arbitration, the refresh request is communicated to the 4041 via the Control Link. The
4041 arbitrates this with CPU or local master accesses to the ISA bus, and sends a Refresh ACK back to the SIPC. At
this point the SIPC performs the ISA refresh (if enabled). When the ISA refresh cycle is complete, the SIPC signals
this to the 4041 via the Control Link. Within the SIPC, the internal HLDA to the DMA controller may then go active if
a DMA request is pending.
Revision 1.0
2/10/95
150
Preliminary
CS4041