F84045 Asiliant Technologies, F84045 Datasheet - Page 65

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Addr
08
Revision 1.0
index
08
6:0
7
Pefrm cntl
function
Bits
Performance control
or more for DX-33 or DX2-66 reduction to 6 or 8 MHz equivalent performance.
CPU hold pulse width. These bits set the amount of time in which the CPU is put in hold following
486 cache flush. 0 = do not flush cache during slow mode HOLD. 1 = flush cache during each slow
2/10/95
each AT bus refresh. Once the count is set, the mode must be enabled by a separate register or the
"Turbo" button (SLOW# pin). The values below are the number of 4045 internal BUSCLKs (see
Index 0Ah) for which the CPU is kept in hold. Normally this occurs about every 15uS.
The programmed value should not exceed the time between refresh cycles. For 15 us refresh rate
and 8.33 MHz 4045 BUSCLK, the maximum usable value is about 120 (14.4 us). Values
approaching 120 (78h) may be needed to reduce the performance of 486DX-33 or DX2-66
systems to 8 MHz equivalent.
mode hold request. Setting this bit to a 1 prevents the 486 from executing from internal cache
during the slow mode hold, which generally will be necessary to successfully reduce the
performance of a DX-33 or DX2-66 system to 8 MHz equivalent.
486 flush
000000 = No hold request (default)
000001 = Minimum speed reduction (one 4045 BUSCLK)
...
111111 = Maximum speed reduction (127 4045 BUSCLKs).
D7
Description
hold width6 hold width5 hold width4 hold width3 hold width2 hold width1 hold width0
D6
Subject to change without notice
Default = 00. Typical setting = 00h for no performance reduction, or F0h
D5
64
D4
D3
D2
Configuration Registers
Preliminary
D1
D0
CS4041