F84045 Asiliant Technologies, F84045 Datasheet - Page 112

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.10.3. Timing Modes
The timing modes are divided into the following parameters:
The burst read, burst write, and single write timings may be set separately for CPU cycles and alternate masters.
Alternate masters include VL bus masters, ISA masters, and DMA cycles. This function allows alternate masters to run
at a slower timing mode. This may be useful for the following reasons:
The three Burst read modes are shown below.
Revision 1.0
The 4041 must generate parity for DRAM write cycles for the alternate master (the CPU parity is used for CPU
The CPU is a more controlled part on the board. Its timing may be able to be assumed better than the worst
The system designer may optimize for the last bit of CPU performance without having to worry about VL-
3-2-2-2 mode
CAS#
DWE#
MEMCS#
4-3-3-3 mode
CAS#
DWE#
MEMCS#
5-4-4-4 mode
CAS#
MA
MA
MA
Burst Read timing (3-2-2-2, 4-3-3-3, or 5-4-4-4)
RAS to CAS timing (1.5 or 2.5(2.0) T states)
Single write timing (1 or 2 WS)
Burst Write timing (3-2-2-2, or 4-3-3-3)
RAS Precharge (2 or 3)
Refresh RAS length (3 or 4)
cycles).
case VL master might be. The CPU may also be located physically closer to the DRAMs and the
4041 than the worst case VL master.
Master timings, and what the end user may install later.
2/10/95
T1
T2
Figure 5.11: Burst Read Timing Modes
T2
Subject to change without notice
T2
T2
111
T2
T2
T2
T2
(final transfer)
Preliminary
Functional Description
CS4041