F84045 Asiliant Technologies, F84045 Datasheet - Page 87

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Subject to change without notice
Functional Description
Depending on system implementation objectives, 0Exxxxh might be a better choice for SMM code and data. During
user mode, the 0Exxxxh area could remain mapped to SMM space (write protected) or be unused. Then case (b) above
would be satisfied without having to make SMM space non-cacheable during SMM. SMM space could remain
cacheable in both L1 and L2 caches.
It should be noted that using shadow RAM for SMM space does not prevent the user mode software from using the
same address ranges for EMS windows. The window addresses used by software are remapped by the CPU paging
mechanism prior to each L1/L2 cache or DRAM access, and thus do not interfere with the SMM address range during
L1/L2 cache and DRAM accesses.
Some CPUs make SMM space non-cacheable automatically, which eliminates any need for the chipset to make SMM
space non-cacheable in L1.
5.6.2.3. Force A20M# High During SMM
A20M# may be forced high during SMM cycles if desired (Index 94h, bit 2). This is not necessary to access SMM
memory since it resides in an area where A20 is low anyway, but it is necessary to access user memory above 1M.
When enabled, this feature will take SMIACT#, invert it, and OR it with the other sources of GATEA20 in the 4041
(keyboard GATEA20 and emulated keyboard GATEA20). This will send a SET GATEA20 and RESET GATEA20
code across the link to the 4045 upon entry and exit from SMI mode. If the internal GATEA20 was already high, no
codes are sent. This feature is not available (and not necessary) for CPUs which use SMIADS# instead of SMIACT#.
5.6.2.4. Soft Reset Redirection
Section 5.3.1 describes CPU reset redirection to SMI. For additional information on reset in general, see section 4.2.
5.6.2.5. Port 26/27 Configuration Register Accesses
Since SMM mode may be entered at any time and cannot be disabled by normal user code, there are possibilities of
splitting a port 22/23 access with an SMM call. If the SMM code accesses configuration registers (which is almost
always will) this will interfere with the user mode port 22/23 access.
To solve this problem, a second window into the configuration register space is provided for SMM mode. Port 26 is
the address port, 27 is the data port. There is a separate address storage register for port 26, and a separate "accessed
bit" for ports 26/27. Accesses through ports 26/27 access the same configuration registers as ports 22/23.
SMM code
should always use ports 26/27. User code should always use ports 22/23.
5.6.2.6. Shadowing Port 70
I/O port 70 is the index pointer into the Real Time Clock/CMOS RAM, and is write only in the SIPC. To allow SMM
code to access the RTC/CMOS RAM, port 70 is shadowed and readable through configuration register 96h.
To access the RTC/CMOS RAM, the SMM code should read index register 96h (through ports 26/27), access port 70
& 71 as necessary, then write the original value back to port 70.
5.7. CPUs Supported
CPUs with a 486 bus are supported, including those with write back caches and SMM support.
There is no configuration register where the CPU type is written. Instead, each feature which requires different
operation in the 4041 for different CPUs is controlled separately. This is because of the wide variety of CPUs, and the
expected evolution of CPUs in the future.
Revision 1.0
2/10/95
86
Preliminary
CS4041