F84045 Asiliant Technologies, F84045 Datasheet - Page 47

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
32
33
Revision 1.0
3:0
4
5
6
7
1:0
7:2
Bits
Memory Decode #0 Size and Destination
this register and program Index 3Ch to disable the MEMCS0# output signal. Memory Decode #0 can
be used for generating MEMCS0#, creating a hole in local DRAM, forcing an internal LDEV# signal
for local bus slaves that don't generate LDEV#, creating a non-cacheable area, or controlling the
WB/WT mode of L1 cache in a selected local or non-local address range.
Range Size
(Reserved).
Hole in DRAM
Local bus area.
(Reserved).
Memory Decode #0 Attributes.
Cache Mode. This affects the cache mode regardless of the cycle's destination. The CHIPSet does not
(Reserved)
2/10/95
support caching any memory other than DRAM (which could be SMM memory), however.
0000
0001
0010
0011
0100
0101
0110
0
1
0
1
00
01
10
11
Description
64K byte range
128K byte range
256K byte range
512K byte range
1Mbyte range
2Mbyte range
4Mbyte range
Range is allowed in DRAM
DRAM within this range is disabled.
disabled.
Force the LDEV# signal for this range. Accesses to this range will be on the local
Use default cache status for this area (based on destination, etc). The defaults are
Non-Cache. Do not cache the memory in either L1 or L2 cache.
Cache as write through in L1 cache. The L2 cache is unaffected by this mode, and is
Cache in write back mode in L1. The L2 cache is unaffected by this mode, and is
bus. Setting this bit will NOT prevent a local DRAM access. The memory
range must be either outside of the local DRAM decode or bit 5 above must also
be set.
typically: cache DRAM in writeback (if the CPU supports it), do not cache non-
DRAM areas.
cached according to the current L2 mode.
cached according to the current L2 mode. If the selected address range is not
entirely within local DRAM, the L1 WB mode won't work if a local bus master,
ISA Master, or DMA read occurs in the selected range and the target memory is
unable to back off if needed (due to L1 data in the CPU being more current than
the data in the target memory).
Subject to change without notice
Default = 00. Typical setting = 00h if Decode #0 is disabled.
46
0111
1000
1001
1010
1011
11xx
Default = 00. To disable Decode #0, write 00h to
8Mbyte range
16Mbyte range
32Mbyte range
64Mbyte range
128Mbyte range
(Reserved)
Configuration Registers
Preliminary
CS4041