F84045 Asiliant Technologies, F84045 Datasheet - Page 143

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

6.1. SIPC Chip Overview
document apply to the 4035 as well, except where otherwise noted. The 4045 is designed to replace the 4035 in
CS4031 designs, as well as providing additional features useful in CS4041 designs. The term “SIPC” refers to both the
4045 and the 4035.
The SIPC is an 82C206 Integrated Peripheral Controller ("IPC") with additional logic added to reduce signal and/or
chip count of the external logic. "SIPC" can be interpreted to mean "Superset IPC." The following features are added
to the 206 to form the SIPC:
6.1.1. 4045 Added Features
The 4045 includes the following features not available in the 4035:
Revision 1.0
The 4045 is derived from the 4035, with a few features added to support the 4041. The 4045 features described in this
WBACK# signal. Accepts the WBACK# output signal from the 4041. This pin was reserved on the 4035.
Additional LREQ/LGNT pairs. 2nd and 3rd sets are available by changing the functions of other pins.
Arbitration Lock added. Prevents HOLD from going active during clock speed changes.
Misbehaved ISA master fix. HOLD will not go inactive until MASTER# is high.
A10:15 decode input pin. Allows 16 bit decode of internal IO. Shared with SA19 pin.
RTC IRQ output. Available on the IGNNE# pin when PWRGOOD is inactive.
RTC Password Protect. PS/2 style via Port 92h (same as in CS4021).
Ability to disable the port 92 reset function to allow redirection to SMI in the 4041.
DMA clock divider allows 14.3MHz clock to be used as a source.
Port 26/27. SMM configuration register access window.
Mouse Interrupt. The mouse interrupt is optionally sent to the 4045 across the control link.
SRESET arbitration mode. This mode controls the CPU reset and HOLD arbitration, allowing the CPU to
IPC Reset Disable. A configuration bit allows the reset to the IPC core to be blocked. This is used to retain
ISA Refresh Disable. Allows ISA refresh to be disabled while DRAM refresh remains enabled, resulting in a
14MHz crystal oscillator circuit and divider
DMA clock divider from SCLK
32KHz crystal oscillator circuit
System reset logic
System arbitration logic including support for local bus masters
ISA bus hidden refresh logic
Performance control logic to emulate an 8MHz PC/AT
DMA controller address generation logic
SA17:19 buffering
A20M# generation
486 floating point error logic
Speaker interface
Control link to communicate with the 4041 or 4031
be reset only when it is in HOLD.
the IPC registers during a 0 volt suspend (suspend to disk).
small performance benefit and allowing a TTL buffer to be eliminated if ISA refresh isn't required.
2/10/95
6. 84045 Functional Description
Subject to change without notice
142
Preliminary
Functional Description
CS4041