F84045 Asiliant Technologies, F84045 Datasheet - Page 71

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

4.3. Arbitration
The 4045 contains most of the arbitration logic. It arbitrates between the CPU, local bus masters, DMA, and ISA
masters. Refresh is always hidden, and occurs when either the CPU or local master has control of the bus.
Local bus masters are supported in accordance to the VL-Bus standard. The 4045 will preempt the local bus master off
of the bus when an unmasked DMA request occurs. The 4035 SIPC provided one set of LREQ# / LGNT# pairs,
allowing more to be created in an external PAL. This is the default mode for the 4045, but it may also be configured to
provide 2 or 3 LREQ# / LGNT# pairs.
The SIPC arbitration logic may be locked to prevent the CPU from going into HOLD when switching CPU clock
frequencies. S-series CPUs may not respond properly to snoop cycles or HOLD requests when the internal CPU VCO
frequency has not yet stabilized following a change in the input clock frequency.
For further information, see Sections 5.4 and 6.5.
4.3.1 Control Link
As noted in the pin descriptions (Section 2), a simple control link is used for communication between the 4041 and
4045. 4041 LOUT is connected to 4045 LIN, and 4045 LOUT is connected to 4041 LIN.
The following events are communicated from 4045 to 4041:
The following events are communicated from 4041 to 4045 using bit-serial event codes:
4.4. Refresh
The AT-compatible Timer 1 in the 4045 generates refresh requests internally to the 4045. The 4045 arbitrates refresh
requests with CPU reset requests, DMA and ISA Master requests (DREQ# inputs), and local bus master requests
(LREQ# inputs). When the 4045 is ready for a refresh operation to proceed, it signals this to the 4041 via the control
link (LIN and LOUT signals). The 4041 then arbitrates the refresh request with CPU activity (DRAM and/or ISA Bus
accesses). When the 4041 is ready for ISA refresh to proceed, it acknowledges the refresh request via the control link
back to the 4045. The 4041 performs the DRAM refresh cycle and the 4045 performs the ISA bus refresh cycle. When
the 4045 has completed the ISA bus refresh, the 4045 signals this to the 4041 via the control link. The DRAM refresh
may occur before, during, or after the ISA refresh.
During ISA bus refresh, the 4045 drives REFRESH#, MEMR# and SA0:7. DRAM refresh is always CAS-before-RAS
(no external refresh address needed). In addition, refresh is always hidden, i.e., the CPU is allowed to continue running
during refresh (HLDA inactive). As long as the CPU doesn't try to access local DRAM or the ISA Bus, there is no
conflict. In particular, the CPU may continue to perform primary and/or secondary cache hit cycles and local bus slave
accesses while a refresh operation is in progress. If the CPU tries to access local DRAM or the ISA Bus during a
refresh operation, READY# and BRDY# are withheld and the CPU cycle is delayed as needed to allow the refresh to
complete. The CPU can access local DRAM as soon as the DRAM refresh cycle is finished, even if the ISA refresh is
still in progress (as will usually be the case).
For further information, see Sections 5.10.4 and 6.7.
Revision 1.0
Refresh Request (normal or ISA Master)
Refresh Complete
DMA Address Strobe
Refresh request acknowledge
Interrupt Acknowledge cycle
CPU Reset Request
Keyboard controller A20 Gate
Keyboard and mouse interrupts (if using internal keyboard/mouse controller)
2/10/95
Subject to change without notice
70
System Level Functions
Preliminary
CS4041