F84045 Asiliant Technologies, F84045 Datasheet - Page 53

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
45
46
47
80
Revision 1.0
Index
44
45
46
47
3:0
6:5
7:6
See register 44
See register 45
0
1
2
3
4
5
6
7
IDE timing B
IDE timing B
IDE timing
IDE timing
Function
Bits
IDE Timing A Command Recovery and Address Setup
I/O recovery time for IDE commands, Timing A. Selects the minimum number of clocks which
Address setup time to IDE commands, Timing A. Selects the minimum number of clo cks between the
(Reserved)
IDE Timing B Read and Write pulse Widths
IDE Timing B Command Recovery and Address Setup
EventA Selection 0: Interrupts.
Setting these bits to a 1 will enable the specified occurrence to generate an EventA, which normally
restarts TimerA. EventA has no other function. TimerA, in turn, can automatically slow the CPU
clock or trigger an SMI, or both. If the bit is a 0, the specified occurrence will be ignored. The events
selected indicate system activity, and that the system should not be slowed down. IRQs are detected
by the corresponding INTA cycle. INTR is detected by a high level.
IRQ0 (Timer Tick)
IRQ1 (Keyboard)
IRQ3,4,5, or 7 (serial and parallel ports)
IRQ6 or 14 (floppy and hard disk)
IRQ9 or 13 (video or coprocessor)
IRQ8,10,11,12, or 15 (Misc Interrupts)
INTR. Any Time INTR goes high (indicating an unmasked interrupt)
NMI. A low to high transition in the NMI pin.
2/10/95
A
A
IDEIOR# and IDEIOW# must remain high between accesses. Used only by the local bus IDE
timing state machine. Encoding is as follows:
address being setup and the command going active. The timing begins when the default values
are forced onto the address and CS pins, or from the start of T1 if SBHE# is not set to provide A2
(A2 provided from the CPU).
0000
0000
0001
0010
0011
00
01
wrA3
wrB3
D7
Description
16
24
1
2
3
4
1
wrA2
wrB2
D6
Subject to change without notice
asuA0
asuB0
wrA1
wrB1
D5
0100
0100
0101
0110
0111
52
4
4
5
6
7
asuA0
asuB0
wrA0
wrB0
D4
10
11
inacA3
inacB3
rdA3
rdB3
D3
1000
1000
1001
1010
1011
inacA2
inacB2
rdA2
rdB2
8
8
10
12
14
D2
2
3
inacA1
inacB1
Configuration Registers
rdA1
rdB1
Preliminary
D1
1100
1100
1101
1110
1111
inacA0
inacB0
rdA0
rdB0
D0
12
16
18
20
22
CS4041