F84045 Asiliant Technologies, F84045 Datasheet - Page 90

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.8. CPU Write Back Cache Snooping
When a CPU with an internal write back cache is used, that cache must be snooped ("peaked into") for local memory
cycles which are initiated by any master other than the CPU itself. This includes cycles initiated by VL-Bus masters
and cycles initiated by the 4041 on behalf of ISA masters and DMA. On a read, the CPU may contain the only valid
copy of the data and must be allowed to write the data back out to secondary cache or local DRAM. On a write, the
previous data may have been cached in the CPU and must be invalidated.
When a master other than the CPU owns the bus, an EADS# will be generated along with the ADS# for all memory
read and write cycles. The EADS# is generated by the initiator of the local bus cycle (the VL-Master or the 4041).
HITM# is generated by the CPU as a result of the snoop. It is driven at the end of the first T2, and may be sampled at
the end of the 2nd T2. The 4041 may sample HITM# either at the end of the second T2 or at the end of the third T2 (to
accommodate different CPU delays). If it is low, the CPU contains dirty data within that cache line. The current
master is then removed from the bus, the CPU is taken out of HOLD, and allowed to write back the dirty data into the
cache and/or DRAM. This will occur as a standard burst write, and is handled by the DRAM and cache controller the
same way that burst writes normally are. The CPU is put back in HOLD when the write back is finished, and the
current master reinitiates the cycle. Using the WBACK# output, the 4041 determines when to allow a writeback
operation to begin after receiving HITM#.
The "L1 write back" configuration bit determines whether the DRAM and cache controller wait for the HITM# signal
when a master other than the CPU has the bus.
Revision 1.0
CPUHOLD
CPUHLDA
address
EADS#
BRDY#
cache read
cache write
DRAM read (-3-3-3)
HITM#
CRD#
ADS#
ADS#
EADS#
HITM#
CRD#
BRDY#
CWE#
BRDY#
CAS#
BRDY#
2/10/95
gets bounced off by WBACK# (HITM#)
VL-Master initiates cycle &
Figure 5.1 L1 Write Back Cache Snoop
Subject to change without notice
Dirty Snoop with Write Back
(low for 4 clocks)
<-- HITM# Sample point
Clean Snoop
89
CPU does write back
4th BRDY#
VL-Master asks again
Preliminary
Functional Description
CS4041