F84045 Asiliant Technologies, F84045 Datasheet - Page 149

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Other Arbitration functions, which are each described below, are:
6.5.3.1. Hidden Refresh arbitration
Hidden Refresh is arbitrated with the DMA controller, since they must be mutually exclusive. The hidden refresh may
occur while the CPU or a local master is in control. Unlike DMA and local masters, hidden refresh does not require the
CPU to go into HLDA state. Hidden refresh and an ISA bus cycle are further arbitrated in the 4041, since an ISA
refresh cannot occur at the same time as another ISA cycle, and the 4041 is the ISA bus controller for CPU or local
master cycles.
6.5.3.2. CPU reset arbitration
The CPU reset is arbitrated with the CPU HOLD signal. The CPU will not be reset while it is in hold, although this is
generally not a problem for 486 CPUs.
The 4045 (unlike the 4035) has an option to reverse this function. When this mode is enabled, the CPU will not be
reset until it IS IN HOLD. This mode is specifically for the SL enhanced CPUs, which take M / IO#, D / C#, and W /
R# high as soon as they receive a RESET or SRESET. This will turn any cycle into a memory write, which could
cause severe problems if the CPU happens to be doing a memory read or code fetch at the time of the reset (which
some programs are known to do). When CPU reset is used to return the CPU from Protected Mode to Real Mode, as
was necessary with software originally developed for 80286-based systems, it is essential not to corrupt the contents of
DRAM or caches.
When a CPU reset is requested, a HOLD request will be generated. The reset will occur when both HOLD and HLDA
are active. The rest of the arbitration logic will function as normal, which means that the DMA controller or VL master
may be granted the bus, or already have the bus when the CPU is being reset. CPU cache snoop cycles can safely be
ignored at this time since the CPU cache will be flushed and disabled upon coming out of RESET. CPUs with an L1
write back cache will handle the SRESET as an interrupt instead of resetting the CPU, and will continue to accept
snoop requests.
This mode is controlled by register 0C bit 3. A 0 selects the original mode. A 1 selects the SL mode. System resets
(initiated by PWRGOOD going high) will be sent to the CPU as normal, without arbitration.
6.5.3.3. VL bus preemption by DMA
The LREQ# and LGNT# signals support a preemptive protocol for the VL-Bus masters. If a DMA HOLD occurs while
a VL-BUS master has the bus, LGNT# is driven back high, requesting that the local master give up the bus. The local
master will take LREQ# back high to indicate that it has given up the bus.
6.5.3.4. Performance Control HOLD
The performance control HOLD request (Index 08h) is ORed with the other sources of HOLD, but does not enter into
the arbitration. A DMA cycle or ISA master may gain access to the bus during a performance control HOLD without
waiting for it to finish.
Revision 1.0
Hidden Refresh arbitration with DMA.
CPU reset arbitration with HOLD
Performance control HOLD (DeTurbo Mode)
Arbitration Lock when the CPU VCO is not stable.
WBACK# pin removing the CPU HOLD.
Misbehaved ISA master fix (waiting for MASTER# to go high before giving control to the CPU or VL master)
2/10/95
Subject to change without notice
148
Preliminary
Functional Description
CS4041