F84045 Asiliant Technologies, F84045 Datasheet - Page 95

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

For a single bank of data RAMs, CA2 and CA3 are supplied by the 4041 and are switched rapidly during a burst.
These address bits are the most time critical for doing a -1-1-1 burst with a single bank.
When two banks of SRAMs are installed, A2 is encoded on the CRD# and CWE# signals, and each bank is supplied
with a separate CA3 signal, which has staggered timing to allow maximum SRAM access time. (CS4021 operates this
way, also.)
The following table is a guideline for what SRAM speeds are required at various frequencies and timing modes.
Additional tradeoffs of performance vs. SRAM speed are also possible.
The tag RAM may be 8, 9, or 11 bits wide. The tag width affects only the cacheable address range of the DRAM in the
secondary cache. A wider tag is required for a small cache to achieve the same cacheable area. Cacheability is a
cost/feature issue which is determined by the customer.
Revision 1.0
Table 5.12: TAG SRAM Configurations
Table 5.13: Suggested Cache Timing Modes and RAM Speeds
128K bytes
256K bytes
512K bytes
Frequency
Cache Size
64K bytes
1M byte
33MHz
40MHz
50MHz
64K, 256K, & 1M 9 bit tag is blank because there are no common 9 bit RAMs in this size. They are valid options.
2/10/95
x8 & x9 RAMs may be used for 64K, 256K, and 1M caches, but half of the chip (1 address line) is not used.
Tag Depth
# banks
Table 5.11: Data SRAM Configurations
16K
32K
Single
Single
Single
Single
Single
64k
4K
8K
Dual
Dual
Dual
Dual
Dual
128K bytes
256K bytes
512K bytes
Cache Size
64K bytes
1M
* Maximum addressability of the 4041 is 256M for local DRAM.
Qty
2
1
2
1
2
Configurations in BOLD are the most common
Read Timing Write Timing Data RAM
Unused tag bits MUST BE PULLED UP. 10K is sufficient.
2-1-1-1
2-2-2-2
2-1-1-1
2-2-2-2
3-2-2-2
2-1-1-1
2-1-1-1
3-2-2-2
2-1-1-1
3-2-2-2
16Kx4
32Kx8
64kx4
4Kx4
8Kx8
Type
Subject to change without notice
8 bit Tag
Qty
Data RAMs, single bank
8
4
8
4
8
cacheability
128M
16M
32M
64M
8M
2-1-1-1
2-1-1-1
2-1-1-1
3-2-2-2
3-2-2-2
2-1-1-1
3-2-2-2
3-2-2-2
3-2-2-2
3-2-2-2
128Kx8
256Kx4
16Kx4
32Kx8
64Kx4
Type
94
Qty
1
1
-
-
-
32Kx9
8Kx9
Type
20nS
25nS
25nS
25nS
20nS
20nS
20nS
25nS
15nS
25nS
-
-
-
9 bit tag
Qty
16
16
Data RAMs (dual bank)
8
8
8
cacheability
128M
16M
32M
64M
-
Tag RAM
8Kx8 or 16Kx4
20nS
20nS
25nS
20nS
25nS
15nS
20nS
20nS
12nS
20nS
128Kx8
32Kx8
64Kx4
8Kx8
Type
Qty
3
2
3
2
3
read timing is loose
16Kx4
32Kx8
64Kx4
read timing is tight
4Kx4
8Kx8
Type
Preliminary
11 bit Tag
Functional Description
Comments
cacheability
512M *
128M
256M
1G *
64M
CS4041