F84045 Asiliant Technologies, F84045 Datasheet - Page 128

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Either timer can be used as either a system inactivity detector or periodic SMI generator or both. Whenever a timer
times out, it automatically restarts at the programmed value and continues counting. Each timer will produce timeout
events repetitively until disabled by software via Index 88h (Timer A) or 8Ah (Timer B). One possible usage of the
two timers is to let Timer A detect long-term system inactivity (e.g., 15 minutes) and let Timer B assist in stopping the
CPU clock again after each IRQ0 Timer Tick interrupt (usually 18 times per second, with 1 ms needed by software for
interrupt processing). In that usage of Timer B, some kind of power management software, either SMI-based or non-
SMI, would need to disable Timer B in response to new system activity other than Timer Tick interrupts.
5.14.1.1. Power Management for Non-SMI CPUs
For non-SMI CPUs, the power management is done in hardware. This basically consists of running at full speed or
reduced speed, and possibly stopping the CPU clock. Initialization software would setup the following:
The hardware will switch to the slower clock when the timer times out, indicating an idle system.
The hardware will switch back to full speed when a wake up event occurs.
While the slow clock is running the hardware may optionally stop the CPU clock when a HALT is executed.
Typical events which reset the activity timer:
Typical wake up events:
A multifunction pin, STPCLK#, may be programmed to indicate the speed mode (full or slow). This may be used to
switch an external clock generator PLL instead of using the internal clock divider. Since the PLL can switch slowly,
this will allow non-SMI CPUs with internal PLLs to be frequency switched.
Algorithm:
Revision 1.0
Activity timer lengths (amount of idle time before switching to the slower clock).
What events reset each activity timer.
What events resume to full power.
What events restart the clock when stopped.
Frequency of the slow clock.
Whether to stop the CPU clock on a HALT.
Keyboard I/O port access
Floppy or hard disk I/O po rt access.
Any interrupt acknowledge other than the system timer.
Any alternate master or DMA cycle.
Any interrupt acknowledge other than the system timer.
Go to slow speed:
Stop Clock
Restart clock
Return to full speed:
2/10/95
TimerA times out (no system events occur)
CPU executes a HALT while in slow speed mode.
Any INTR or NMI or external source
Wake up event (INTA other than IRQ0, push button, NMI, master/DMA access)
Subject to change without notice
127
Preliminary
Functional Description
CS4041