F84045 Asiliant Technologies, F84045 Datasheet - Page 82

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The video areas each have a shadow ram enable bit. There are not separate bits for read and write. The address areas
and bit definitions are listed below.
Flash ROM support under the Microsoft Chicago operating system requires that the shadow RAM be enabled on a
32KB boundary in the Exxxxh and/or Fxxxxh ranges. This is because Chicago only allocates a 64KB segment for the
Plug-and-Play software, and programming the flash ROM requires accessing the ROM and shadow RAM (for the
program) at the same time. To accomplish this, the 4041 has a separate set of shadow RAM bits (Index 1Dh) which are
OR'd with the original set. They are available only for the Exxxxh and Fxxxxh ranges, but on a 32KB boundary.
To program the flash ROM, the appropriate flash shadow bits should be turned on in register 1Dh, followed by turning
off the appropriate bits in registers 19h and 1Ah. (Doing this in reverse order may prevent CPU access to the program,
causing a system crash or unrecoverable application error.) For additional information, refer to Index register 1Dh
description.
High 1MB ROM. Memory reads from the 1MB range at the very top of the 4GB address space (FFFxxxxxh) always
activate ROMCS# and MEMR# and cause data steering from XD-bus (for ROM), regardless of any shadow RAM or
ROMCS or other bit settings. (ROM data on the XD bus is driven onto the ISA bus as well into the 4041.) This is a
fixed decode, allowing the BIOS ROM to begin executing properly after any CPU reset. The first CPU instruction
fetch following a CPU reset comes from FFFFFFF0h and normally is a far jump into the 000Fxxxxh area. Usually the
ROM doesn't receive address bits higher than A17 or A18, so ROM accesses in the FFFFxxxxh range normally map to
the same physical ROM space as accesses in the 000Fxxxxh range (when shadow RAM is disabled). Memory writes to
the top 1MB range generate ROMCS# and MEMW#, even if no ROMCS enable bits are set as ones (Index 1Bh = 00h).
Since the system BIOS normally is 64KB, the size of the high ROM area may be reduced to 64KB instead of 1MB in a
future revision of the 4041.
256MB Address Space Limitation. The total memory address space accessible by the CPU's 32-bit address is 4GB
(4096 MB, where M = 1024K and K = 1024). However, to make the most efficient use of available pin count on the
4041, CPU address bits A28, A29, and A30 do not connect to the 4041. A31 is connected to allow detection of
coprocessor I/O accesses and is included in memory address decoding. Thus, the 4041 effectively divides the 4GB
address space into two 2GB subdivisions, each of which is further divided into eight 256MB blocks. Since the ISA bus
only receives A0-23, the ISA bus effectively is replicated at 16MB intervals throughout the 4GB address space, subject
to cycle claiming by L2 cache, DRAM, VL slaves, or ROM.
Within the lower 2GB subdivision (A31 = 0), DRAM and L2 cache may occupy up to the full 256MB of each 256MB
block. Any holes in DRAM or space left over from the top of DRAM to the top of 256MB may be occupied by ISA or
VL memory. DRAM or ISA accesses above the first 256MB go to the same physical DRAM or ISA memory as
accesses in the lowest 256MB, effectively making only the first 256MB useful in a system implementation. In fact,
incoherency can arise between the CPU cache and external DRAM if the CPU cache contains data from different
256MB blocks, one of which is then written to.
Revision 1.0
A0000-AFFFF (graphics mode area)
B0000-BFFFF (text mode area)
2/10/95
Table 5.6: DRAM Shadow Bit Encoding
DRAM
Enable
Read
0
0
1
1
DRAM
Enable Reads Writes
Write
0
1
0
1
DRAM
DRAM DRAM enabled
Subject to change without notice
ISA
ISA
DRAM enabled
ISA disabled
ISA disabled Shadow RAM, write protected.
Writes
Cache
81
Shadow RAM, read/write
Move ROM to RAM
Memory on ISA bus
When Used
Preliminary
Functional Description
CS4041