F84045 Asiliant Technologies, F84045 Datasheet - Page 133

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

NMI. NMI is generated by the 4041. It causes an event on a low-to-high edge.
IRQs. The IRQ pins do not enter the 4041. Instead, the 4041 detects specific IRQs via the interrupt acknowledge
cycle. This simplifies the software greatly, since it does not have to know which interrupts are enabled in the 8259
logic in the 4045. Interrupt acknowledges are generated by the 4041 and sent across the link to the 4045. The 4045
returns the vector on the second INTA. The event logic will look at the second INTA (where A2 is 0) and pick up the
vector from XD0:7 when INTA# goes back high. The vectors returned by the two 8259s are programmable, although
DOS systems always program them the same way (IRQ0:7 produce vectors 08:0Fh and IRQ8:15 produce vectors
70:77h). The only thing this logic must do when it receives a vector is figure out which interrupt controller it came
from. The location of the second interrupt controller is automatically captured in register 87h. The 4041 compares this
to the upper 5 bits of the vector. If it is equal it is IRQ8:15, otherwise it is IRQ0:7. Normally the value is programmed
to 0111 0xxx when running under DOS, but the value automatically tracks the value written into the interrupt
controller. This allows the value in 87h always to match the value currently being used by software. Windows, for
example, changes the interrupt vector base in INTC2 to 58h, then changes it back to 70h upon return to DOS.
Alternate Master. This event is detected by HLDA going high. This will occur when any alternate master owns the
bus, including VL Masters, ISA Masters, and DMA cycles. It does not go active for refresh cycles.
External Pins. Two external pins may be used to cause events. These are multifunction pins, which may be used for
many functions. The are programmable as active high or low, and level or edge detected to cause an event. Two bits
program the mode for each.
EventA. EventA causes Timer A to restart. EventA is the final OR of all of the individual events which are currently
enabled. It may be used as an event input for EventB. This would mean that EventB would occur anytime EventA
occurs PLUS any additional events selected for EventB (the individual selections for EventB are more limited than for
EventA).
I/O port Events. There are many standard peripherals at known locations. These are decoded with fixed decodes.
Some of these are enabled in groups. For instance all of the COM and Parallel ports are enabled together, while a
separate register determines which addresses to look at. The addresses are given in the tables below. The two
programmable I/O port ranges may also be selected as an event. See the Programmable I/O decode section for details
on programming this.
Memory Access Events. Memory accesses are less common as system events. The CS4041 allows accesses to VGA
memory to be system events. Within the VGA event, the A0000 and/or B0000 area may be selected.
Revision 1.0
Table 5.38: External Pin Event Modes In Index Register 8Fh
External Pin Mode
2/10/95
00
01
10
11
Table 5.39: Event Fixed I/O Address Ranges
* I/O port 3F2h is not included for the floppy because it is accessed
often by the timer tick interrupt to shut off the motor. Including
it would falsely indicate floppy activity.
Keyboard Controller
IDE Controller(s)
Parallel Ports
Floppy Disk
COM Ports
Function
Active High level Triggered.
High to low edge Triggered.
Active Low level Triggered.
Low to high edge Triggered
VGA
Subject to change without notice
Function
132
See Parallel Port Table
3B0:3BB, 3C0:3DF
3F0:3F1, 3F3:3F5*
I/O Address Range
See COM table
See IDE table
Event pulse on high to low edge
Event pulse on low to high edge
60 and 64
Event Active while high
Event Active while low
Event Duration
Preliminary
Functional Description
CS4041