F84045 Asiliant Technologies, F84045 Datasheet - Page 118

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.12.1. Connections and Signal Generation
The following signals are specific to the fast IDE controller:
The following signals have special significance during IDE accesses:
The following signals are also used by the IDE interface:
5.12.1.1. IDEIOR#, IDEIOW#, & IDEEN# Generation
IDEIOR# and IDEIOW# are the OR of the ISA IOR# and IOW# and the local bus IDE state machine signals. The ISA
IOR# and IOW# are sometimes generated internally by the 4041 (CPU or VL master) and sometimes generated
externally (DMA and ISA master).
The IDE state machine generates the IDEIOR# and IDEIOW# only for data port accesses (1F0 for the primary IDE
address). The ISA state machine generates them for all other cycles.
IDEEN# is generated from the ISA IOR# and IOW# signals when they are accessing the IDE devices, and from the
local bus state machine when it is accessing them.
5.12.1.2. IDECS0#, IDECS1#, XA0:1, and SBHE# Generation
IDECS0#, IDECS1#, XA0:1, and SBHE# are all forced to a default state when not in use. This default state is that of
an access to the data port (1F0 on the primary IDE address) and provides the setup time for IDE data port reads. This
allows the IDE access to start earlier in the bus cycle. The default states are high for IDECS1# and low for all of the
others.
When a cycle goes to the ISA bus the signals revert to their normal values. IDECS0# and IDECS1# are address decodes
and XA0:1 and SBHE# come from the ISA state machine. When the DMA controller or ISA master has control of the
bus the IDECS0# and IDECS1# are address decodes and XA0:1 and SBHE# are sourced externally throughout the
entire cycles.
SBHE# is a special case. When this function is enabled (the normal case) SBHE# becomes A2 during IDE cycles.
When an IDE I/O port is accessed, A2 is substituted for SBHE#. This occurs only for IDE addresses which are enabled
for the 4041 IDE controller, and only when the CPU or VL master has the bus. This function may be disabled and A2
supplied from the CPU A2. This provides less IDE address setup, but preserves the function of SBHE#.
5.12.1.3. P3F7D7
This is an input only bit to the 4041. During I/O reads from location 03F7 and 377 this bit is used for D7. This is to
allow the floppy disk to provide this bit while the hard disk is providing bits 0:6. This is a shared I/O port on the
original IBM AT disk controller card. It is now gaining almost as much fame and folklore as the infamous GATEA20
signal.
Revision 1.0
IDEIOR#
IDEIOW#
IDECS0#
IDECS1#
IDEEN
P3F7D7
XA0:1
SBHE#
IOCHRDY
IOCS16#
SYSRESET
IRQ14
2/10/95
I/O read strobe
I/O write strobe
IDE Chip Select 0. Command and data. 1F0-1F7 at primary IDE address.
IDE Chip Select 1. Control. 3F6-3F7 at primary IDE address.
#
IDE ready. Has spe cial timing for IDE data transfers.
IDE IOCS16#. May be forced active internally.
IDE reset (inverted)
Subject to change without notice
IDE buffer enable.
Port 3F7 bit 7. Disk Change from the floppy.
IDEA0 and 1. Normally forced low.
IDEA2. Normally forced low.
IDE interrupt
117
Preliminary
Functional Description
CS4041