F84045 Asiliant Technologies, F84045 Datasheet - Page 147

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

6.4. GATEA20
The SIPC generates A20M#. In response, the 486 CPU performs the actual gating of address bit A20. This gating is
needed for software compatibility with the 8088 and 8086 at address FFFF:10h and above.
Within the SIPC itself, there are two sources for A20M#:
The 4031 and 4041 OR together all of their sources for GATEA20, and send a code across the link whenever this signal
changes. The main sources in the 4041 are the keyboard controller GATEA20 (external, internal, or emulated) and the
SMM GATEA20 function.
The A20M# output pin is shared with the TEST# input. At power up this pin is floated and remains that way until
index register 09 bit 4 is written to a 1. This bit disables the test input and begins driving A20M#. Until the bit is set
to a 1, an external pull-up resistor keeps the pin high, preventing the SIPC from going into test mode, and holding
A20M# high to the CPU to allow it to boot.
6.5. Arbitration
6.5.1. Arbitration Overview
The arbitration logic for the system is contained in the SIPC. It performs the following functions:
The following signal pins are involved in arbitration:
6.5.2. VL Master Arbitration
In the 4045, VL master arbitration for three sets of LREQ/LGNT signals is similar to the arbitration performed with an
external PAL in a 4035 system, but more elegant. (PAL implementations generally use a simple scheme in which VL
masters keep pre-empting each other rapidly). When a VL master owns the bus and another VL master requests it, the
arbitration logic will take the first LGNT# high, wait for the LREQ# to go high, then give the bus to the second master.
In order to prevent VL masters from continuously preempting each other and dropping system performance, a master
will not be preempted by another VL master until it has had the bus for 31 T states. This is enough to do several
average memory accesses, but not long enough to cause latency problems. The 31 clocks start when the VL master
gets control of the bus. The DMA controller will preempt immediately, without waiting for the clocks.
Revision 1.0
Control link codes from the 4031 or 4041
Port 92 bit 1.
Arbitrates between the CPU, local bus masters, and the internal DMA controllers.
Arbitrates between 2 or 3 sets of VL masters (optional, in 4045 only)
Puts the CPU in HOLD to slow it down when performance control (DeTurbo) is enabled.
Arbitrates between CPU HOLD and CPURESET (in two different ways).
Arbitrates between the DMA controller and hidden refresh.
Preempts VL masters when a DMA cycle is pending.
Brings the CPU out of hold to perform a cache write back following a snoop.
Prevents the CPU from going into HOLD to allow for a speed switch (through a config bit).
HOLD and HLDA for the CPU
LREQ0# and LGNT0# for local bus masters
LREQ1# / LGNT1# and LREQ2# / LGNT2# if enabled.
DGNT# indicating the DMA controller has the bus.
WBACK# for CPU write back cache support.
2/10/95
Subject to change without notice
146
Preliminary
Functional Description
CS4041