F84045 Asiliant Technologies, F84045 Datasheet - Page 111

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.10.2. Address Muxing
Revision 1.0
Table 5.21: Address Multiplexing
Interlv bit
Page Size
Table 5.20: CPU Address Assignments For Interleaving and Non-Interleaving
Col n
Row n
decode
Interleave
MA
10
11
12
0
1
2
3
4
5
6
7
8
9
Address
CPU
2/10/95
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2
3
4
5
6
7
8
9
Column
(all sizes)
address
10
11
23
25
2
3
4
5
6
7
8
9
-
Indicates that the address bit appears on this column address bit.
Indicates that the address bit appears on this row address bit.
Indicates that this bit is included as part of the bank decode as programmed in t h e starting address register.
Indicates that this bit is included as part of the bank decode, and is decoded as a 0 for even numbered banks and a 1 for
decode
decode
decode
decode
decode
decode
decode
no intrl
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
256K
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
23, 24 or 26
11 or 20
12 or 22
20 or 21
22 or 24
odd numbered banks.
address
choices
Row
interleaved
13
14
15
16
17
18
19
25
Interleave
decode
decode
decode
decode
decode
decode
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 0
256K
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
Subject to change without notice
non-int
256K
no intrl
decode
decode
decode
decode
decode
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 0
Row 9
2K
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
Col 9
11
12
13
14
15
16
17
18
19
20
x
-
-
-
1M
interleaved
Interleave
interlv
decode
decode
decode
decode
110
256K
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 0
Row 9
Row 1
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
Col 9
2K
1M
20
12
13
14
15
16
17
18
19
20
11
x
-
-
Row Address assignment for:
and Col 10
Row 10
no intrl
Row11
decode
decode
decode
1 or 4M
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 0
Row 9
non-int
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
Col 9
4M
4K
20
12
13
14
15
16
17
18
19
21
22
23
-
interleaved
and Col 10
Interleave
Row 10
Row11
decode
decode
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 0
Row 9
Row 1
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
Col 9
1 or 4M
4M
interlv
4K
20
22
13
14
15
16
17
18
19
21
24
23
12
& Col 11
Row 10
Row 11
Row 12
no intrl
decode
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 0
Row 9
Col 10
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
Col 9
16M
non-int
16M
4K
20
12
13
14
15
16
17
18
19
21
22
24
25
-
Preliminary
Functional Description
interleaved
Interleave
& Col 11
Row 10
Row 12
Row 11
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 0
Row 9
Row 1
Col 10
Col 0
Col 1
Col 2
Col 3
Col 4
Col 5
Col 6
Col 7
Col 8
Col 9
16M
interleave
16M
4K
20
22
13
14
15
16
17
18
19
21
24
26
25
12
CS4041