F84045 Asiliant Technologies, F84045 Datasheet - Page 54

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
81
82
83
Revision 1.0
index
index
80
81
82
83
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
WakeupA
WakeupA
function
function
EventA
EventA
Bits
EventA Selection 1: I/O and Memory Accesses.
Disk accesses. Which ones are determined by the Index 86h.
Serial or Parallel Ports. Which addresses are determined by Index 86h.
Keyboard controller (60h & 64h)
Video Memory (A0000h to BFFFFh)
Ext0 Pin (A multifunction pin). Polarity, etc, selected elsewhere.
Master (HLDA high). Any VL Master, ISA Master, or DMA cycle
Programmable I/O address 0 (see Indexes 28:2B)
Programmable I/O address 1 (see Indexes 2C:2F)
WakeA Event Selection 0. Interrupts
Setting these bits to a 1 will enable the specified occurrence to generate WakeA, which may generate
an SMI and/or switch the CPU clock back to full speed. If the bit is a 0, the specified occurrence will
be ignored. The events selected indicate an occurrence which should bring the system back to
operating speed due to either the operator or an external event. All events are detected identically to
EventA and the bit positions are identical. Only INTR, NMI (i.e., IOCHCK#), and Ext0 are detectable
as WakeA events while the CPU clock is stopped.
IRQ0
IRQ1
IRQ3,4,5,7
IRQ6,14
WakeA event selection 1. I/O and memory accesses
Identical selections as register 81.
Disk
Serial/Parallel Ports
Keyboard
Video Memory
2/10/95
prog IO 1
prog IO 1
NMI
NMI
D7
D7
Description
6
prog IO 0
prog IO 0
INTR
INTR
D6
D6
Subject to change without notice
IRQ8,10:12,15
IRQ8,10:12,15
master
master
D5
D5
4
5
INTR
7
5
6
7
53
IRQ9,13
IRQ9,13
Ext0
Ext0
D4
D4
IRQ9,13
IRQ8,10,12,15
NMI
4
Master
Programmable I/O 0
Programmable I/O 1
video mem
video mem
IRQ6,14
IRQ6,14
D3
D3
irq3,4,5,7
irq3,4,5,7
D2
D2
kb
kb
Ext0 pin
com/lpt
com/lpt
Configuration Registers
IRQ1
IRQ1
Preliminary
D1
D1
IRQ0
IRQ0
disk
disk
D0
D0
CS4041