F84045 Asiliant Technologies, F84045 Datasheet - Page 83

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

All memory accesses to the higher 2GB (A31 = 1) go to the ISA bus or high ROM unless the access is claimed by a
VL memory slave. As in the lower 2GB, the 4041 replicates address mapping at 256MB intervals.
The 256MB replication interval in the 4041 doesn't apply to VL memory slaves if they decode the full 32-bit address.
VL memory potentially can reside uniquely anywhere in the entire 4GB space that doesn't overlap local DRAM. VL
memory slaves can also claim ROM cycles, including accesses to the high 1MB area. Assertion of LDEV# during a
ROM cycle doesn't necessarily prevent ROMCS# from being asserted, but it prevents MEMR# and MEMW# and gives
the cycle to the VL slave.
5.5.2.1. Programmable Memory Decodes
Two programmable decodes provide attributes for specific memory ranges.
programmable bits:
The starting address must be on a decode "size" boundary. For instance, if the decode is to be 1 megabyte, it must be
placed on a 1meg boundary. The Size bits simply determine which address bits to ignore, according to the following
table:
The attribute bits determine how the memory decodes are used. If all are 0 the decode has no effect. The bits control
functions independently, and any combination of the bits may be used (although not all combinations are necessarily
useful).
Hole in DRAM Bit
This bit disables the DRAM decode for the memory range, allowing a hole to be placed in DRAM. This would be used
if an I/O card on the VL or ISA busses required a specific memory range, which would normally be in DRAM. If the
programmed memory range does not hit the local DRAM, the bit will have no effect. While this function will work in
the 640 to 1M range, there are specific bits for that range which are generally more versatile.
Revision 1.0
Starting address (must be on a "size" boundary)
Size (64K, 128K, 256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, 64M)
Caching Status.
Hole in DRAM.
Force to VL bus
2/10/95
Table 5.7: Programmable Memory Decode Size and Placement
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Size
Bits
Subject to change without notice
Decode
128M
128K
256K
512K
16M
32M
64M
Size
64K
1M
2M
4M
8M
82
Placement
Boundary
128M
128K
256K
512K
16M
32M
64M
64K
1M
2M
4M
8M
A31, A27:16
A31, A27:17
A31, A27:18
A31, A27:19
A31, A27:20
A31, A27:21
A31, A27:22
A31, A27:23
A31, A27:24
A31, A27:25
A31, A27:26
Address Bits
A31, A27
Decoded
The decodes have the following
Preliminary
Functional Description
CS4041