F84045 Asiliant Technologies, F84045 Datasheet - Page 120

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Most of the parameters may be selected differently for different drives. Older drives cannot be run as fast as newer
drives in general, and some newer drives are faster than others. The 4041 allows two sets of timing parameters to be
specified and allows each of the 8 drives to select which one it uses. In a typical system which will allow for only 2
drives, this allows each drive to be programmed separately. Drives 0, 1, 2, and 3 may also be programmed to skip the
local bus accesses and access the data port from the ISA bus. This would be required if the drive only supported 8 bit
data accesses for some reason. IOCS16# will be sampled by the ISA bus. It is ignored, and assumed active for the data
port by the fast cycle logic.
The internal logic determines which drive is being accessed according to the following table.
Three parameters control when the command goes active: The T state start bit, which sets the earliest start at the end of
either the first T2 or the second T2, the Address Setup selection, which sets the minimum number of T states that the
address signals are setup (forced to their "default" states) before the command may go active, and the Command
Recovery, which sets the minimum high time of the command. The Address Setup and command recovery parameters
may be set differently for different drives.
Normally even if the address setup is set to a large number (4 is the maximum) the command may go active at the end
if the first or second T2. This is because the default states of the address signals are generally present for many T states
before the IDE access. An internal counter constantly monitors how long the default states have been held, and is
checked at the start of the IDE data port access. The only time when the commands must wait for the address setup is
following an ISA bus cycle (where the ISA address is present until near the end of the local bus cycle) and when the
IDE cycle follows a DMA/ISA master cycle (where DGNT# was high). Even at these times the time-out will likely be
achieved.
The Command Recovery Time is also constantly monitored by a counter. An active IDE command resets the counter,
and it starts counting when both are inactive. A new command will not be issued until the select command recovery
time has been met. The command recovery time only delays a data port access.
The Command Recovery Time is also used between commands on a 32 bit I/O operation.
The Read and Write command pulse widths are fairly self explanatory. These parameters are only used for data port
accesses.
5.12.2.2. Command/Control Registers
All I/O ports of the IDE drives other than the data port are accessed by standard ISA cycles. The only difference is the
steering of the external data bus drivers. The IOR# and IOW# ISA commands are copied onto the IDEIOR# and
IDEIOW# pins. IDEEN# goes active as described below. On read cycles, SDIR0 and SDIR1 do not go low, since the
data will be driven from the IDE buffers.
Revision 1.0
2/10/95
Table 5.26: Determine Which Drive Is Active
Drive #
Drive 0
Drive 1
Drive 2
Drive 3
Drive 4
Drive 5
Drive 6
Drive 7
Subject to change without notice
Data Port Being
Accessed
1F0
1F0
5F0
5F0
170
170
570
570
119
Drive Select Port
Port 1F6 Bit 4=0
Port 1F6 Bit 4=1
Port 176 Bit 4=0
Port 176 Bit 4=1
Port 5F6 Bit 4=0
Port 5F6 Bit 4=1
Port 576 Bit 4=0
Port 576 Bit 4=1
& Value
Preliminary
Functional Description
CS4041