F84045 Asiliant Technologies, F84045 Datasheet - Page 91

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.9. Secondary Cache Controller
The secondary (L2) cache controller has the following features:
The cache consists of "cache lines," each of which contains 16 data bytes and a tag address indicating what general area
in DRAM the data bytes came from. As an example, a 256KB cache contains 16K cache lines (K=1024).
CPU address bits map onto the cache as follows:
Secondary cache may be either single bank or dual bank. Dual-bank cache provides a performance advantage because
the two banks can be interleaved on dword boundaries (CPU address bit A2 determines bank selection). Single-bank
cache may offer a better balance between system cost and cache size for lower cost or entry level systems.
Secondary cache may be either write through (WT) or write back (WB), although WB mode normally will provide the
best system throughput. In WT mode, DRAM writes that are cache hits go simultaneously to both the cache and the
DRAM. In WB mode, such writes go only to the cache and thus take less time to execute. The updated data remains
in the cache until a subsequent line fill is needed due to a cache read miss, at which time the "dirty" cache line is
written back out to DRAM before the new cache line is filled. In either mode, line fills occur only on read miss cycles,
never on writes (i.e., the 4041 does not "allocate on write"). The process of writing a "dirty" cache line back out to
DRAM is also referred to as a "castout" operation and is performed as a four-dword burst write. The CPU or alternate
master is held in wait states while the castout is occurring.
Table 5.8.1: CPU Address Bit Usage
* To save pins, the 4041 doesn't connect to CPU address bits A28-A30.
Revision 1.0
Highest line select bit
Highest tag bit, 8-bit tag
Highest tag bit, 9-bit tag
Highest tag bit, 11-bit
tag
A0-A1 (actually BE0-3 on the bus) address a specific byte within a dword.
A2-A3 select a specific dword within a cache line. Each cache line has 4 dwords.
A4 through An select a specific cache line, where "n" depends on the cache size. Table 6.8.1 lists the highest CPU
A(n+1) through Am are stored in the tag field of the cache line during a line fill, and subsequently compared with
address bit used for cache line selection ("An").
the tag field to determine cache hit or miss. "m" depends on tag size as well as total cache size. Table 6.8.1 lists
the highest CPU address bit used for tag addresses. This, in turn, determines the maximum cacheable range, as
shown in Table 6.8.2. Tag bit 0 is used as the "dirty bit" for write-back cache mode and is not used for write-
through mode. This means that only 7, 8, or 10 CPU address bits are used for 8, 9, or 11-bit tag sizes,
respectively.
Direct Mapped.
Standard SRAMs
External Tag RAM
Internal tag comparator
Operation up to 50MHz
16 byte line size
64K, 128K, 256K, 512K, and 1M cache size
Write back or write through
Single bank or dual bank (word interleaved) cache.
2-1-1-1, 2-2-2-2, or 3-2-2-2 reads. (2-2-2-2 mode for single bank only)
0ws or 1ws writes
2-1-1-1 or 3-2-2-2 burst writes.
2/10/95
64KB
A15
A22
A23
A25
128KB
A16
A23
A24
A26
Subject to change without notice
256KB
A17
A24
A25
A27
90
512KB
A27*
A18
A25
A26
A27*
1MB
A19
A26
A27
Preliminary
Functional Description
CS4041