F84045 Asiliant Technologies, F84045 Datasheet - Page 107

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

On a CPU write cycle to the test window, data from index 23 and 24 gets written to the tag RAMs. The timing is
identical to that of a "Write Hit Clean". It will be either 1 or 2 wait states depending on the "Tag Write Timing" bit
(index 20 bit 0). Before doing the write to the test window, the CPU writes indexes 23 and 24 with the desired data.
Note that there is one tag location for every 16 bytes of data. The Tag RAMs get A4 as the lowest address bit. An
access to any byte within the 16 byte, word, or dword within the 16 byte tag line will read or write the tag RAM.
Consecutive tag RAM locations should be accessed by incrementing the CPU address by 16 bytes (10H).
The cache mode bits must be set as indicated for the Data SRAM test mode. The data RAMs are disabled during this
time.
The following occurs when Tag test mode is enabled:
To size the Tag RAM:
To write a tag location:
To read a tag location:
5.10. DRAM Controller
Features:
Revision 1.0
Reads within the test window will latch the tag data at the end of T2. The cycle will be 0WS. The CPU will read
Writes within the test window will write the test data to the tag with the same timing as a Write Hit Dirty (1 or 2 wait
The tag comparator is disabled.
No castouts occur.
Memory accesses outside the test window go to DRAM, the AT bus, etc. and are not cached.
No line fills occur
The test window decode is substituted for the tag hit signal.
The DRAM sees test window accesses as cache hits.
Writes will not go to DRAM regardless of WRMODE.
The cache size bits and tag width bits are ignored, except to determine the window size, as indicated in the above
The KEN# signal is not effected by this mode.
Set the test window to the desired location. If it is in the lower 1M, set the cache size to 512K to get the full 512K byte
Set the cache mode bits as indicated above.
Disable the 486 internal cache to avoid getting fooled.
Set the Tag Test mode ON.
Test to see if and where the SRAM repeats itself, incrementing by 10H for each tag location, reading and writing the
To test the RAM:
Set the test window to the desired location. If it is in the lower 1M, set the cache size to 512K to get the full 512K byte
Set the cache mode bits as indicated above.
Disable the 486 internal cache to avoid getting fooled.
Set the Tag Test mode ON.
Write the desired data to Indexes 23 & 24.
Write to the desired memory location in the test window.
Read the desired memory location in the test window. Ignore the data.
Read the data from Indexes 23 & 24.
garbage data. RDY# will be returned, not BRDY#.
states)
table.
test window size. To test for a 1M cache size, the windows must be at 1M.
tag as indicated below:
test window size. A 256K window may be used by programming any other cache size if it is already known
that the cache is less than 512K.
Do a RAM test within the test window, reading and writing the tag as indicated below:
Up to 8 banks of DRAMs (4 double bank SIMMs, etc.)
Page mode and Page interleave .
256K, 1M, 4M, and 16M deep DRAMs supported.
Direct drive RAS.
Direct drive CAS, DWE, and MA for up to 2 banks.
Hidden refresh with RAS staggering.
2/10/95
Subject to change without notice
106
Preliminary
Functional Description
CS4041