F84045 Asiliant Technologies, F84045 Datasheet - Page 162

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The IRQ1 pin is always an input on the 4045, and the pin is ignored (bypassed via the Control Link) when using the
internal keyboard controller in the 4041.
6.14. Port B and Speaker logic
The SIPC contains the following bits of Port B (IO port 61)
When reading port 61h, the 4045/4035 and 4041/4031 respond as follows:
In the 4045, bit 4 toggles on each Refresh Request (Timer 0 output pulse). The bit continues to toggle even when ISA
refresh is disabled.
Refer to the Port 61h register description in Section 3 for further functional description of Port 61h.
6.15. Manufacturing Test Modes
The 4045 and 4035 have two test modes to support board-level manufacturing test:
The Hi-Z mode is entered simply by driving PWRGOOD low. (PSRSTB should be pulsed low while PWRGOOD is
low to reset the IPC functions, but this probably won't affect pin tri-stating.) While PWRGOOD is low, all outputs are
placed in high-impedance state except the 14MHz output (which is driven low) and the 32 KHz output (which remains
responsive to the 32 KHz input).
The connectivity test mode is activated as follows:
Timings aren't critical. Setup and hold times of 50 ns minimum should be adequate.
Revision 1.0
SIPC drives bits 0-5 onto the XD bus, and the 4041/4031 passes them through transparently to the CPU local data
bus. Bits 2 and 3 have no function in the 4045 other than readback. Bits 4 and 5 are read-only.
SIPC drives bits 6-7 to zero on the XD bus, but the 4041/4031 drives the proper values onto the CPU local data
bus. Bits 6-7 originate in the 4041/4031 and are not implemented in the 4045/4035. Bits 6 and 7 are read-only.
Putting all outputs in a high-impedance state (Hi-Z)
Checking each pin's soldering connection (AND tree)
Drive PWRGOOD low, then pulse TEST# low momentarily (A20M# pin).
While TEST# is low, drive hex code FEh onto XD7:0. This code is latched on the rising edge of TEST#.
2/10/95
Table 6.3 SIPC Port B bits
Bit
0
1
2
3
4
5
6
7
ENB RAM PCK
Tmr Gate 2
EN IO CK
Spkr Data
IO Write
Subject to change without notice
-
-
-
-
ENB RAM PCK
Tmr Gate 2
161
EN IO CK
Spkr Data
REF Det
IO Read
OUT2
-
-
(In the 4041/4031)
(In the 4041/4031)
from ref det circuit
(In the 4041/4031)
(In the 4041/4031)
from tmr 2 output
Speaker circuit
Speaker circuit
Usage
Preliminary
Functional Description
CS4041