F84045 Asiliant Technologies, F84045 Datasheet - Page 77

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.2.2. Clock Inputs
The 84041 receives the following clocks:
CLKIN. Main clock input. Source for CLK2OUT, SCLKOUT, CPUCLK, and BUSCLK.
CLK2. 2x system clock. Used only for the 2x DRAM CAS state machine.
SCLK. 1x system clock. Used for all CPU related functions.
CWS#. Advanced 1x CPU clock. Used for the cache write enables.
5.3. Reset and GATEA20
The 4041 receives SYSRESET as an input from the SIPC chip. This input resets all registers and state machines to a
known state. The clock divider circuit (the 2x to 1x circuit) operates while SYSRESET is active since the SIPC
receives its clock from the 4041 and needs SCLK to generate the resets.
Both the CPURESET and A20M# (final GATEA20 to the CPU) pins are contained in the SIPC chip, but the 4041 chip
provides information to the SIPC for both functions. This information is sent to the SIPC over the control link. The
4041 performs the following functions:
The keyboard GATEA20 and KBRESET come from one of three sources, as selected from the following table:
5.3.1. CPU Reset and SMI
The Intel S series CPUs must not have an SRESET occur during SMM operation, or shortly following SMM operation.
To avoid this, the 4041 may optionally redirect all CPU restart requests to cause an SMI rather than reset the CPU.
(See Index 94h bit 4 and Index 0Ch bit 0.) System management mode may then perform the CPU reset function by
jumping to the reset vector upon exiting SMM mode.
Revision 1.0
Table 5.2: GATEA20 & KBRESET Source.
Detects a CPU Shutdown
Detects a CPU reset request from the internal or external 8042.
Optionally detects Port 92 bit 0 transitions to reset the CPU.
Optionally emulates the 8042 CPU reset request.
Detects a change o n the GATEA20 signal from the internal or external 8042
Optionally emulates the 8042 GATEA20 signal, speeding up the operation.
Detects a 1 being written to Index 39h bit 6 (special CPU reset).
2/10/95
External 8042
Internal Keyboard Controller
Emulated Fast GATEA20 logic
External 8042
Internal Keyboard Controller
Emulated Fast KB reset
GATEA20 Source
KB reset Source
Subject to change without notice
Internal KB
Ctrl enable
X
X
76
0
1
0
1
GATEA20
Emulate
0
0
1
-
-
-
KB RESET
Emulate
0
0
1
-
-
-
Preliminary
Functional Description
CS4041