F84045 Asiliant Technologies, F84045 Datasheet - Page 105

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Freezing the Cache Directory . While the cache is operating in write back or write through mode, the directory can be
frozen to prevent new data from going to the cache. Writes will occur as normal, including updating the dirty bit if
necessary. Read misses will simply not update the cache data or tag RAMs. This bit may be turned on and off at any
time except when initializing the cache. A possible use is for preventing large data moves from thrashing the cache, or
trying to cheat on a benchmark.
5.9.10. Tag & Data SRAM Testing
The 4041 has test modes for both the cache tag and data RAMs. The purpose of these modes is for the BIOS software
to determine the size of the cache, and test its functionality before enabling it.
Testing the data RAMs basically makes them appear as static RAM within the test window. The CPU reads and writes
to them as if they are just a static RAM bank. Testing the tag is a little more involved since the CPU does not have
direct access to the tag data. The tag data is stored in a register within the 4041, which the CPU reads and writes
through I/O ports 22 and 23.
There are two choices for the test window. One option places it in the bottom megabyte of the address space, allowing
it to be used in REAL mode. The other places it at the 1Meg point, and must be used in protected mode. Register 22
bit 3 determines which mode is used. The addresses are as follows:
The only effect of the cache size bits in either test mode is to determine the window size when the window is in the
bottom meg. This allows more available DRAM when testing a cache that is 256K or smaller. The 512K test window
is required for tag sizing, to determine whether the cache is 256K or 512K, however.
Note that the CPU addresses go directly to the tag and data RAMs (through an F244 for the data RAMs). The test
mode does no mapping of any kind. When there is a 512K test window in the bottom meg, the address mapping is
shifted a little, as follows:
5.9.10.1. Data SRAM Testing
When Data SRAM Testing mode is enabled, the cache appears as static RAM within the test window. The tag
comparator is disabled (by virtue of the cache being disabled) and hits are forced whenever a memory cycle is done
within the test window. All timing is the same as normal cache hits, as programmed in the configuration registers.
Writes have the timing of a Write Hit Dirty. The DRAM controller will see these cycles as cache hits, and will be
activated. All cycles outside the test window will act like a non-cacheable area. No line fills, etc.
Revision 1.0
Freezing and Unfreezing the Cache Directory.
Flip the FRZCDIR bit as needed.
2/10/95
Table 5.15: Cache Test Window Location
Table 5.16: 512K Cache Test Mode Mapping When In The Lower Meg
Reg 22 bit 3
0
0
1
80000-9FFFF
20000-7FFFF
CPU address
64K, 128K, 256K
Cache Size bits
Subject to change without notice
512K
All
104
40000-7FFFF (256K to 512K area)
20000-9FFFF (128K to 640K area)
100000-17FFFF (1M to 2M area)
Test Window address range
Physical SRAM address
00000-1FFFF
20000-7FFFF
Preliminary
Functional Description
CS4041