F84045 Asiliant Technologies, F84045 Datasheet - Page 134

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.14.7. I/O Restart
I/O restart allows CPUs with SMM capability to trap specific I/O operations and later restart them. This may be used to
power-down peripherals, then re-initialize them when an access attempt is made. It may also be used to emulate a
device, but this is a less common usage.
I/O cycles are detected on the local bus. If a cycle is to be restarted, it does not generate an ISA cycle. Instead, the
internal LDEV# is pulled, and SMI# is issued. RDY# is returned to the CPU 4 SCLKs after SMI# is generated.
Several fixed I/O ranges may be selected to issue restarts as well as the two programmable ranges. The fixed ranges
are:
Revision 1.0
Table 5.41: Power Management Configuration Registers
index
8A
8B
8C
8D
8E
8F
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
SMI statusA next register
smi enableA global enable
smi EnableB
select which
timerA cntrl
SMI statusB
smm modes
Commands
timerB cntl
Stop Clock
INTA base
Time Base
Shadow70
WakeupA
WakeupA
WakeupB
I/O restart
EXT pins
function
EventA
EventA
EventB
timerA
timerB
COM1or COM2 (3F8:3FF, 2F8:2FF)
Parallel port at 378:37F
Floppy and Hard disk controllers (1F0:1F7 & 3F0:3F7,
The VGA I/O (3B0:3BB, 3C0:3DF)
The keyboard. (60 & 64)
The two programmable ranges.
2/10/95
Table 5.40: Selectable Ranges for Specific Events
IDE Controller Events
Function I/O Address
wakeA event
waitstopack
WakeAfast
stpclk# pin
prog IO 1
prog IO 1
intabase7
smi mode
prog IO 1
IDE1
IDE2
IDE3
IDE4
port70d7
EventA
tmrA7
tmrB7
NMI
NMI
D7
-
1F0:1F7, 3F6
170:177, 376
prog IO 0
prog IO 0
prog IO 0
intabase6
plldelay2
prog IO 0
slowclk2
port70d6
tmrA6
tmrB6
INTR
INTR
Ext 1
IDE2
D6
-
-
Subject to change without notice
IRQ8,10:12,15
IRQ8,10:12,15
intabase5
plldelay1
slowclk1
port70d5
master
master
master
tmrA5
tmrB5
IDE1
Function I/O Address
Halt
Halt
KB
D5
COM Ports Events
COM1
COM2
COM3
COM4
-
SoftResRedir
TimerASlow
I/O Restart
I/O Restart
133
keyboard
intabase4
plldelay0
port70d4
IRQ9,13
IRQ9,13
Stop clk
sloclk0
floppy
tmrA4
tmrB4
VGA
Ext0
Ext0
3E8:3EF
2E8:2EF
3F8:3FF
2F8:2FF
D4
-
stpclk4slow
video mem
video mem
video mem
floppy/HD
WakeupB
WakeupB
intabase3
External1
External1
port70d3
IRQ6,14
IRQ6,14
GenSMI
EXT1 1
DisKen
tmrA3
tmrB3
cksel
SMI
D3
Parallel Ports Events
Function I/O Address
170:177 & 370:377)
LPT1
LPT2
LPT3
ForceA20m flushOnSmm
WakeupA
WakeupA
stopmode
LPT(378)
irq3,4,5,7
irq3,4,5,7
External0
External0
port70d2
lpt1,2,3
EXT1 0
rateA2
tmrA2
rateB2
tmrB2
Stpclk
INTR
NMI
div2
D2
kb
kb
-
3BC:3BE
378:37F
278:27F
StopHaltnslo StopOnHalt
CPU restart Software smi
CPU restart Software smi
port70d1
com3&4
EXT0 1
com/lpt
com/lpt
TimerB
TimerB
GoFast
rateA1
tmrA1
rateB1
tmrB1
INTR
com2
IRQ1
IRQ1
Ext 1
div1
Preliminary
D1
Functional Description
-
smiact pin
com1&2
port70d0
GoSlow
EXT0 0
TimerA
TimerA
rateA0
rateB0
tmrA0
tmrB0
com1
IRQ0
IRQ0
IRQ0
div0
disk
disk
D0
-
-
CS4041