F84045 Asiliant Technologies, F84045 Datasheet - Page 26

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

AEN
TC
DREQ0:3
DACK0:3#
DACK5:7#
SLOW# / LREQ1#
FLUSH# / LGNT1#
ISA Bus (4045)
MEMR#
MEMW#
SMEMR#
SMEMW#
IOR#
IOW#
Revision 1.0
DREQ5:7
96
97
77, 74, 71, 68
63, 56, 53
76, 73, 70, 67
62, 55, 52
12
49
48
94
95
47
46
2/10/95
4
OUT
OUT
IN
OUT
IN
OUT
I/O
I/O
OUT
OUT
I/O
I/O
DMA address enable. High for DMA and refresh cycles, low at all other times,
DMA terminal count. This signal goes high during the final cycle of a DMA
DMA requests. 0:3 are 8 bit channels. 5:7 are 16 bit channels. Any may be used for
DMA acknowledges.
Dual Function pin, determined by a configuration register.
Turbo switch input. Low is slow, high is fast. The Performance Control registers
LREQ1#. Additional VL-Bus master request. Internally arbitrated with the other 1
Dual Function pin, determined by a configuration register.
FLUSH#. This signal, when used, is connected t o the CPU FLUSH# pin. It is used
LGNT1#. Additional VL-Bus master grant.
Memory Read strobe. Connected directly to the ISA bus. Output during DMA
Memory Write strobe. Connected directly to the ISA bus. Output during DMA
Memory Read strobe for the bottom 1Mbyte. Connected directly to the ISA bus.
Memory Write strobe for the bottom 1Mbyte. Connected directly to the ISA bus.
I/O Write strobe. Connected direc tly to the ISA bus. Output during DMA cycles,
I/O Write strobe. Connected directly to the ISA bus. Output during DMA cycles,
which includes when the CPU, local masters and ISA masters have control of the
bus. The main function of this signal is to disable all IO decodes in the system.
transfer. It is used mainly by the floppy disk controller, but may also be used by
other DMA devices.
ISA masters, but 5:7 are preferred because there is less arbitration overhead.
must be set up before this signal has any effect. The purpose is to emulate the
speed of an 8MHz AT for software (mostly games and copy protect schemes)
which assume a certain execution speed.
or 2 LREQ#s.
in conjunction with the performance control. The CPU cache is optionally
flushed each time the CPU is put into HOLD for performance control to better
control the speed of execution.
cycles, input at all other times to generate SMEMR#.
cycles, input at all other times to generate SMEMR#.
Output at all times. This signal is a function of A20:23 and MEMR#, and is low
when all of those signals are low.
Output at all times. This signal is a function of A20:23 and MEMW#, and is
low when all of those signals are low.
input at all other times, to access internal I/O.
input at all other times, to access internal I/O.
Subject to change without notice
25
Preliminary
Pin Descriptions
CS4041