F84045 Asiliant Technologies, F84045 Datasheet - Page 42

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
1D
1E
Revision 1.0
Index
Index
1D
1E
0
1
2
3
4
5
6
7
1:0
2
3
4
5
6
7
dram sec tim
shdw/parity
Function
Function
Bits
DRAM Block Parity Enable and 32KB Shadow Control.
= 0Fh to enable parity checking on all four blocks. This register allows parity to be enabled or
disabled in individual DRAM blocks. Parity checking occurs only if the corresponding DRAM block
is enabled via Index 12h or 13h. See also Index 11h bit 7. 0=Parity not checked. 1=Parity checked.
Block 0 (RAS0# and RAS4#)
Block 1 (RAS1# and RAS5#)
Block 2 (RAS2# and RAS6#)
Block 3 (RAS3# and RAS7#)
Bits 7:4 below provide a means of enabling shadow RAM with 32KB granularity in the Exxxxh and
Fxxxxh ranges. This allows flash ROM programming when only a 64KB memory segment is
available to the software. Shadow RAM is enabled by either these bits or the bits in Indexes 19h and
1Ah. Unlike 19h and 1Ah, these bits enable both reads and writes, both for user mode and SMM.
These bits usually should be turned on before turning off the bits in Indexes 19h and 1Ah to make
sure that the executing program remains accessible.
E0000h-E7FFFh Shadow RAM enable.
E8000h-EFFFFh Shadow RAM enable.
F0000h-F7FFFh Shadow RAM enable.
F8000h-FFFFFh Shadow RAM enable.
Secondary DRAM Timing register.
10h or one speed slower. This register sets the timing mode used for the DRAMs when HLDA is
high, i.e., when DRAM is accessed by a local bus master, ISA master, or DMA transfer.
Read Timing Mode.
RAS to CAS timing
(Reserved)
Write wait states, single write.
RAS Precharge Time.
Write burst Timing.
(Reserved) (Refresh RAS pulse width always uses the register 10h mode)
2/10/95
0
1
00
01
10
0
1
0
1
0
1
0
1
F8shdw
D7
D7
-
Description
Disabled (shadow RAM controlled by Indexes 19h and 1Ah).
Enable Shadow RAM read and write for this area for both user mode and SMM.
3-2-2-2 page hits (default). Va lid only in 2X clock mode.
4-3-3-3 page hits
5-4-4-4 page hits (50MHz)
CAS generated 2 T states (1.5 for 3-2-2-2 mode) after RAS (default)
CAS generated 3 T states (2.5 for 3-2-2-2 mode) after RAS
1 wait state writes.
2 wait state writes.
2 T states of RAS precharge time.
3 T states of RAS precharge time.
-2-2-2 burst write timing (default)
-3-3-3 burst write timing.
write burst
F0shdw
D6
D6
Subject to change without notice
RAS prechg
E8shdw
D5
D5
41
write ws
E0shdw
D4
D4
Default = 00. Typical setting should be same as Index
ParBlk3
D3
D3
-
RAS-CAS
ParBlk2
D2
D2
Default = 00. Typical setting
read burst1
ParBlk1
Configuration Registers
Preliminary
D1
D1
read burst0
ParBlk0
D0
D0
CS4041