F84045 Asiliant Technologies, F84045 Datasheet - Page 84

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Putting a hole in DRAM will also make the range non-cacheable, since only local DRAM is cached. This has the effect
of disabling cache line fills. It will not prevent cache hits if the memory range is already in the cache. If the hole is
placed in DRAM after the cache has already been in use in WB mode, the cache contents should be flushed out by
reading a cacheable memory range twice the size of the cache before setting this bit.
Force to VL-Bus Bit
This bit will force the access to the VL bus by forcing LDEV# low internally. The LDEV# pins will be ignored.
Forcing LDEV# will only take the cycle away from the ISA bus, not the DRAM and cache controller. The Hole in
DRAM bit should also be set to take the cycle away from the DRAM (which will also disable cache line fills).
Cache Attribute Bits
These bits set the cache attributes. Only local DRAM can be cached in the secondary cache, and normally also in the
L1 cache. These bits allow a memory range to be forced to be non-cacheable or write through cacheable. If the range
is not in DRAM it can also be forced to be cacheable in the L1 cache. Each configuration is described below:
Chip Select
The programmable decode may also provide an external chip select. This is done by selecting one of the multifunction
pins to provide a chip select from one of the memory decodes. There is no enable for this function in the memory
decode's registers, since the programming of the multifunction pin is sufficient.
Revision 1.0
00 Default mode. In this mode the decode has no effect on the cache, and the memory takes on the default
01 Non-Cache. In this mode the programmed range is not cached in either the L1 or L2 cache.
10 Write through in L1. In this mode the programmed range is forced to write through in the L1 cache. The
11 Write Back Cache in L1. In this mode the programmed range is forced to write back in the L1 cache, even
dec0 Index
30
31
32
33
cache mode, which is normally set to cache all of DRAM in either write back or write through mode.
L2 cache is unaffected, and is cached according to the current L2 mode. If the CPU contains a write
back cache, the WB / WT# pin of the CPU must be connected to a multifunction pin with this
function selected in order to force it to write through. This mode will force any range to be cacheable
in the L1 cache, even if it is on the ISA bus or VL-Bus.
if the default mode that is programmed on the 4041 is write through. The CPU must be capable of
write back operation, and this mode enabled in the CPU for this bit to have any effect. The WB /
WT# pin of the CPU must also be connected to a multifunction pin with this function selected in order
for this bit to have any effect. This bit does not affect the L2 cache in any way. This mode will force
any range to be cacheable in the L1 cache in write back mode, even if it is on the ISA bus or VL-Bus.
THIS IS VERY DANGEROUS, since the slave must be capable of being backed off during VL or ISA
master/DMA snoops. This should only be done to ISA and VL memory if there is no chance that a
VL master or ISA master or DMA will access the memory. The main use of this bit is to make only a
specific section of main DRAM write back in the CPU.
2/10/95
dec1 Index
34
35
36
37
A23
A31
D7
-
-
Subject to change without notice
VL local
A22
A30
D6
-
A21
A29
hole
D5
-
83
A20
A28
D4
-
-
Size3
A19
A27
D3
-
Size2
A18
A26
D2
-
cache1
Size1
Preliminary
A17
A25
Functional Description
D1
cache0
Size0
A16
A24
D0
CS4041