F84045 Asiliant Technologies, F84045 Datasheet - Page 106

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The tag test registers, Indexes 23 & 24, are actually separate registers for reading and writing. After writing index 23,
reading it back will NOT give the data just written, but will give the value stored in the register during the last read
from the test window with tag testing enabled.
The following occurs when Data SRAM test mode is enabled:
The cache mode bits must be set as follows:
To size the Data SRAM:
To test the Data SRAM:
5.9.10.2. Tag Testing
Tag testing is a little more complicated than data RAM testing. Like the data RAM test mode, tag testing involves the
CPU reading and writing to the test window. The CPU cannot directly read or write the tag RAM, however. Registers
at index 23 and 24 hold the data for tag testing.
On a CPU read from the test window, the tag data is written into index registers 23 & 24 at the end of T2. This is a
0WS read, and the CPU received garbage data. The CPU must read indexes 23 and 24 to get the data.
Revision 1.0
Reads within the test window will read the SRAMs and be at the programmed timing mode.
Writes within the test window will write the SRAMs and be at the programmed timing mode.
The tag is ignored.
No castouts occur.
Memory accesses outside the test window go to DRAM, the AT bus, etc. and are not cached.
No line fills occur
No TAG writes occur
The test window decode is substituted for the tag hit signal.
The DRAM sees test window accesses as cache hits.
Writes will not go to DRAM regardless of WRMODE.
The cache size bits and tag width bits are ignored, except to determine the window size, as indicated in the above
The KEN# signal is not affected by this mode.
Set the test window to the desired location. If it is in the lower 1M, set the cache size to 512K to get the full 512K byte
Set the cache mode bits as indicated above.
Disable the 486 internal cache to avoid getting fooled (or use Page Cache Disable).
Set the Data SRAM Test mode ON.
Test for single or dual bank as follows:
Test the size of the SRAM as summarized below. (This is fairly complex because in dual bank mode the programmed cache
All lower address bits should be checked to verify SRAM integrity.
Set the test window to the desired location. If it is in the lower 1M, set the cache size to 512K to get the full 512K byte
Set the cache mode bits as indicated above.
Disable the 486 internal cache to avoid getting fooled.
Set the Data SRAM Test mode ON.
Do a RAM test within the test window.
Set the Single/Dual bank bit to Dual Bank.
If single bank is installed, bytes 4:7 and C:F of each cache line will not work (the bus will float on reads).
If single bank is detected, switch the Single/Dual bank bit to Single bank.
size affects which CPU address bit is sent to CA2. See note in CA2 section above.) Stop on the first case that works:
table.
ENCACHE = 0
WRMODE=X
test window size. If a 1M cache is to be tested, the window must be at 1M.
Set the cache size to 1M and verify that the RAM does not repeat when changing A16, 17, 18, & 19.
Set the cache size to 512K and verify that the RAM does not repeat when changing A16, 17, & 18.
Set the cache size to 256K and verify that RAM does not repeat when changing A16 & 17.
Set the cache size to 128K and verify that RAM does not repeat when changing A16.
If none of the above works, assume the cache data size is 64K.
test window size. A 256K window may be used by programming any other cache size if it is already known
that the cache is less than 512K.
2/10/95
Subject to change without notice
INITCACHE = 0
105
FRZCDIR = 0
Preliminary
Functional Description
CS4041