F84045 Asiliant Technologies, F84045 Datasheet - Page 76

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.1. DRAM/Cache/ISA Controller Chip
The 4041 controls the local DRAM, secondary cache, and ISA bus.
5.2. Clocks
5.2.1. Clock Generating Logic
The 84041 receives a 1x or 2x clock from an external oscillator on the CLKIN pin and generates the following clocks:
CLKIN goes to a programmable speed reduction divider for slowing the system down. For full speed this divider is
bypassed. The output of the speed reduction circuit is always passed out the CLK2OUT pin. SCLKOUT and
CPUCLK are derived by either dividing by 2 when CLKIN is 2x or sending them out directly when CLKIN is 1x.
1X or 2X clock mode is signaled to the 4041 by a reset strapping option on the NMI pin. While SYSRESET is high,
the NMI pin is an input to the 4041. An external pull-up or pull-down resistor determines the state of the NMI pin
during this time. The pin state is sampled and latched on the falling edge of SYSRESET. If the pin is sampled high,
the 4041 will operate in 1X clock mode. If NMI is sampled low, the 4041 will operate in 2X clock mode. The clock
mode can be verified for test purposes by comparing CLKIN to SCLKOUT. In 1X mode, they will be the same
frequency. The clock mode can also be checked via Index Register 38h, bit 7.
A 10K resistor should be sufficient for the NMI pull-up or pull-down, as long as there are no TTL loads on the NMI
signal. Otherwise, a lower value pull-down may be needed for 2X clock mode. To assure proper detection of the clock
mode, there is a short delay after the falling edge of SYSRESET before the NMI pin becomes driven as the NMI output
signal for the CPU.
5.2.1.1. Speed Reduction Divider
The clock divider is used to provide the slow clock mode. The programming of the divider must not be done while the
slow clock is enabled. The division choices are as follows, with the resulting frequency shown for typical full speed
frequencies. It is programmed in register 8C, bits 6:4.
The power management hardware and/or software selects between the full speed and slow clocks.
Revision 1.0
BUSCLK
CLK2OUT
SCLKOUT
CPUCLK
2/10/95
Table 5.1: Clock Divider
Mode
000
001
010
011
100
101
110
111
5. 84041 Functional Description
ISA bus clock. Normally about 8MHz.
2x clock output. 1x when the CLKIN pin is driven from a 1x oscillator.
1x clock output. Used for the VL bus, 84045, and most of the 84041 logic.
1x clock output for the CPU. May be stopped by power management logic.
CLKIN/10
CLKIN/2
CLKIN/3
CLKIN/4
CLKIN/5
CLKIN/6
CLKIN/8
CLK Out
CLKIN
Subject to change without notice
25MHz
4.167
3.125
12.5
8.33
6.25
(25)
2.5
5
75
33MHz
16.67
4.167
11.1
8.25
6.67
(33)
5.5
3.3
40MHz
13.3
6.67
(40)
20
10
8
5
4
50MHz
16.67
12.5
8.33
6.25
(50)
25
10
5
Preliminary
Functional Description
CS4041