F84045 Asiliant Technologies, F84045 Datasheet - Page 25

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

2.5. 84045 Pin Descriptions
Clocks
14MX1
14MX2
SCLK
Resets
PWRGOOD
CPURESET
SYSRESET
Arbitration
HOLD
HLDA
LREQ0#
LGNT0#
DGNT#
WBACK#
MASTER#
REFRESH#
Revision 1.0
2
3
99
98
21
54
20
19
6
5
8
11
34
59
2/10/95
IN
OUT
IN
IN
OUT
OUT
OUT
IN
IN
OUT
I/O
IN
IN
I/O
14.31818MHz crystal input. Divided internally by 12 for the 8254 clock inputs.
14.31818MHz crystal output. This pin is buffered externally and used as the ISA
1x CPU clock input. Used for arbitration logic, reset generation, and selectively
From the power supply or power on clear circuit.
RESET to the CPU only. Synchronized to SCLK. Connects to SRESET of an S
RESET to the rest of the system. Has the same timing as CPURESET, but is only
HOLD to the CPU. Synchronous to SCLK.
HLDA from the CPU. The 4045 assumes it is synchronous to SCLK.
Bus request from the local masters. Arbitrated with the other two LREQN# signals
Bus Grant to local bus masters. This signal goes low to give control to a local bus
DMA controller hold acknowledge (an output only).
This signal is used to take HOLD to the CPU low for 4 clocks regardless of the state
ISA masters pull this signal low after gaining control of the bus through a DMA
ISA bus refresh signal. The 4045 drives this signal low during refresh cycles.
May also be used as a source for the DMA clock.
bus OSC signal.
divided down to make the DMA clock.
series CPU.
active following PWRGOOD being low. Connects to RESET of an S series
CPU if CPURESET is used for SRESET.
(if used) and with the DMA controllers and CPU for control of the bus.
master. Two additional LREQ/LGNT pairs are provided on multifunction pins.
Multiple sets may also be created externally with a PAL.
optionally preempt a local master off the bus when an unmasked DMA request
occurs.
controller or ISA master has control of the bus. Used for buffer steering and
goes to the 4041. When PWRGOOD is low or SYSRESET is high this pin is an
input to select the SA17:19 configuration. High = SA17:19. Low for alternate
functions.
of the arbitration. It is used to allow a CPU with a write back cache to perform
its write back following a snoop of a DMA, ISA Master, or local bus master
cycle. It also floats address lines A8:9, and A17:23 if a DMA cycle is in
progress to allow the CPU to drive these lines.
channel's DREQ / DACK# signals. When this signal goes low the AEN output
is taken low.
During refresh cycles while an ISA master has control of the bus, the master
drives it low.
Subject to change without notice
24
Indicates that the DMA
Preliminary
Pin Descriptions
The 4045 will
CS4041