F84045 Asiliant Technologies, F84045 Datasheet - Page 152

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The following timing diagram shows a hidden refresh cycle. Hidden refresh wins the arbitration with DMA, since there
is no pending DMA request. RefAck is the output of the Link Input logic of the SIPC, and indicates that 4041 has sent
a Refresh Acknowledge over the link, allowing the refresh to proceed. During the hidden refresh sequence, DGNTIN#
goes active (the DMA HLDA input to the DMA/Refresh arbiter). DGNT# is withheld until the hidden refresh is
finished.
For master refresh, no arbitration need be done since the current master is requesting the refresh. When the ISA master
pulls REFRESH# low, the SIPC performs the refresh by driving SA0:7 with the refresh and driving MEMR# and
SMEMR#. The SIPC also pulls LOUT low for the duration of REFRESH# active to indicate to the Sprite chip that a
refresh is occurring. In response to SIPC LOUT, the 4041 performs a refresh for local DRAMs.
The SIPC drives both MEMR# and SMEMR# low for refresh cycles, regardless of the address on the upper bits (for
normal bus cycles SMEMR# is only driven when A20:23 are all low).
Two configuration bits control refresh:
The “normal operation” setting for both of these bits should be a 1.
Revision 1.0
Register 09 bit 2 controls the Refresh Request signal from Timer 1 of the 8254 equivalent logic in the IPC core.
This bit blocks the Refresh Request signal when a 0, which is the power up default. The main purpose of this is to
avoid refreshes immediately after power up. The 8254 timer does not receive a reset of any kind, and continues to
operate after a hardware reset. Software should set this bit to a 1 for normal operation. All refreshes will be
disabled when this bit is a 0, including both DRAM and ISA refresh cycles.
Register 09 bit 3 controls ISA refresh. This function exists in the 4045 only (not the 4035). ISA refresh is always
enabled in the 4035. When this bit is a 0, ISA refreshes do not occur. All of the arbitration described above still
occurs, since part of this arbitration is what signals the DRAM controller to do a refresh, and the 4041 does not
know whether or not ISA refresh is enabled. When the refresh is granted by the 4031/4041, the 4045 immediately
signals that the ISA refresh is complete.
TMR1
RefPend
LOUT (from SIPC)
RefAck (from link)
REFRESH#
SA0:7
MEMR#
DMA HRQ
DGNT#
2/10/95
(internal)
Figure 6.2 Hidden Refresh Timing
Subject to change without notice
Wins arbitration with HOLD
A DMA Requests
151
Preliminary
Functional Description
DMA Granted
after refresh
CS4041