F84045 Asiliant Technologies, F84045 Datasheet - Page 124

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The write data hold time should be set as follows (see the timing table above):
5.13. Multifunction Pins
Several pins on the 4041 may take on multiple functions. This section describes each function and which pins may be
programmed for what functions.
5.13.1. CPU Functions
WB / WT#. Output. This pin is used by CPUs with L1 write back caches. It is sampled at the same time as the first
RDY# or BRDY# of a CPU cache line fill. It is stored in the TAG information in the CPU for future write cycles to
that cache line. WB / WT# must be valid at the end of the first T2 for 0 wait state L2 cache hits. The default state is
high (Write Back). It may be forced low by either Programmable Memory decode being set to write through mode, or
by the BIOS area being set to Write Through.
WPROT#. Output. Write Protect. This is an input for some future CPUs. When this signal is sampled low with the
first RDY# or BRDY# of a cache line fill, the line is marked as Write Protected in the tag. The 4041 drives this signal
asynchronously with the Write Protect decode. It must be asynchronous to be valid by the end of the first T2. It is
driven for all memory cycles, regardless of read or write (the CPU samples it on writes).
5.13.2. Cache and DRAM Functions
CACHECS. Output. Cache Chip Select. Active high. Used to power-down the cache RAMs between cycles. The
generation of this signal is described in the cache controller section.
MEMCS#. Output. Memory Chip Select. This signal controls the optional data bus buffers for the DRAMs. The
generation of this signal is described in the DRAM controller section.
MA12. DRAM address bit A12. Used for 16M deep DRAMs with 13/11 addressing (16Mx4).
5.13.3. VL-Bus Functions
LDEV1#. Input.
LDEV2#. Input. Additional LDEV# inputs. Logically ORed internally with LDEV0#, which is a dedicated pin. An
external OR function (physical AND gate) may be used instead to perform the same function.
5.13.4. SMM and Power Management Functions
EXT0. Input. External Event 0 for the power management logic. Used in various ways to cause system events, etc.
May also generate an SMI. See the Power management section for details.
EXT1. Input. External Event 1. See above.
CLKSPEED. Clock Speed select. This pin goes high to select the slow clock. Used for an external synthesizer.
14.3MHz. 14.31818MHz input. May optionally be used for the power management time base.
Revision 1.0
33MHz:
40 & 50MHz:
2/10/95
Always 0
If any Mode 0 timing drive is attached and is using Timing A or Timing B, set to 1, else 0.
Subject to change without notice
123
Preliminary
Functional Description
CS4041