F84045 Asiliant Technologies, F84045 Datasheet - Page 80

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.5.1.1. Programmable I/O Decodes
There are two programmable I/O decodes. These may be used to provide a chip select or strobe to external logic or as
an event detection to the power management logic. The I/O restart may also be enabled for these ranges. Each has a 16
bit starting address and an 8 bit mask, and the following attribute bits:
The address decode for A15 through A0 may be programmed. The upper and lower address bits may be masked in
different ways to provide the decode size/range. For bits A6:A0 there is a three bit size selector which determines
which address bits to decode. Within these bits the address must be contiguous. For bits A10:7 there are individual
mask bits. This allows a decode to be active for non-contiguous spaces such as COM1 and COM2. Address bits
A15:11 have a common mask bit. The programming is summarized in the following tables:
A multifunction pin may be programmed to provide the I/O chip select. The function of the chip select is selected by
the 4 bits in the I/O decode's registers. The bits are as follows:
These bits select whether the pin will be active for I/O reads, I/O write, both, or neither.
Revision 1.0
Activate for Reads
Activate for Writes
Force to VL bus (Forces LDEV# internally).
Generate chip select for I/O reads
Generate chip select for I/O writes
Generate chip select for ISA masters
Select asynchronous chip select, or read and/or write strobe (ANDed with I/O commands)
2/10/95
Table 5.4: I/O Decode Lower Bit Mask (A6:0)
Size
Bits
Table 5.5: I/O Decode Upper Bit Mask (A15:7)
000
001
010
011
100
101
110
111
Mask Bit
A15:11
A10
A7
A8
A9
Subject to change without notice
(bytes/ports)
Decode Size
128
16
32
64
1
2
4
8
Repeats At
1024 ports
128 ports
256 ports
512 ports
all upper.
79
Placement
Boundary
128 bytes
16 bytes
32 bytes
64 bytes
2 bytes
4 bytes
8 bytes
any
Address Bits
Ignored
A15:11
A10
A7
A8
A9
Address Bits
Decoded
A6:0
A6:1
A6:2
A6:3
A6:4
A6:5
A6:6
none
Preliminary
Functional Description
CS4041