F84045 Asiliant Technologies, F84045 Datasheet - Page 27

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

IOCHRDY
Address Bus (4045)
SBHE#
SA0:7
A8:9
SA17 / LREQ2# 60
SA18 / LGNT2#
SA19 / IOCS#
A17:19
A20:23
A20M# / TEST#
Revision 1.0
35
45
79, 78, 75, 72, 69, 66, 64, 61
44, 43 I/O
57
42, 41, 40
39, 38, 37, 36
14
2/10/95
58
I/O
OUT
I/O
I/O
I/O
I/O
I/O
I/O
OUT
ISA bus ready. Input during DMA cycles to add wait states to the command strobes.
ISA bus byte high enable. Driven only during DMA cy cles. For 8 bit DMA
ISA bus address bits 0:7. Direct drive of the ISA bus. Outputs during DMA cycles
Local bus address bits 8:9. Connected to the CPU local bus. Outputs during DMA
Dual Function.
ISA bus address bit SA17. Direct drive of the ISA bus. Output at all times except
LREQ2#. Additional VL-Bus master request. Internally arbitrated with the other 1
Dual Function.
ISA bus address bit SA18. Direct drive of the ISA bus. Output at all times except
LGNT2#. Additional VL-Bus master grant.
Dual Function.
ISA bus address bit SA19. Direct dri ve of the ISA bus. Output at all times except
IOCS#. Internal I/O chip select. When high the internal I/O is disabled. May be
Local bus address bits 17:19. Connected to the CPU local bus. Outputs during
Local bus address bits 20:23. Connected to the CPU local bus. Outputs during
Connected to the CPU A20M# pin. This is the OR of the emulated keyboard
Output during accesses to the DMA controller registers to optionally add a wait
state.
(channels 0:3) it is driven with the inverse of A0. For 16 bit DMA (channels
5:7) it is driven low.
and refresh cycles. Inputs at all other times.
cycles. Inputs at all other times.
ISA master cycles, where it is floated. It is driven from A17.
or 2 LREQ#s.
ISA master cycles, where it is floated. It is driven from A18.
ISA master cycles, where it is floated. It is driven from A19.
connected to a decode of A10:15, which may be provided by the 4041.
DMA cycles, inputs (to drive SA17:19) at all other times.
DMA cycles, floated at all other times.
SMEMR# or SMEMW#.
GATEA20 and the fast GATEA20 (port 92 bit 1). After reset this pin is the
TEST# input. If pulled low the 4045 will go into test mode. It becomes the
A20M# output after a configuration bit has been set, at which time it begins
driving the pin and ignoring it as an input. A 10K pull-up should be connected
to this pin to prevent test mode from being entered and to keep A20M# high at
power up.
Subject to change without notice
26
Also used as inputs to generate
Preliminary
Pin Descriptions
CS4041