F84045 Asiliant Technologies, F84045 Datasheet - Page 146

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Subject to change without notice
Functional Description
In the 4045 the port 92 reset may be disabled, allowing the 4041 to redirect it to SMI. The 4041 will also redirect the
other sources of the CPU restart by not sending the link code.
The SIPC interlocks CPURESET and the CPU HOLD signal to prevent both from occurring simultaneously. This is
required for a 386 CPU. If the CPU is currently in HOLD when the reset request occurs, the reset is delayed until after
the HOLD is removed. Likewise if a hold request is issued during the CPU reset sequence, it is delayed until after the
CPURESET is removed. The 4045 also contains an option to reset the CPU only when it IS IN HOLD. This is for the
SL enhanced CPU, as described in the arbitration logic section.
CPURESET is 16 SCLKs long (minimum) for soft resets. The falling edge always occurs from the rising edge of
SCLK.
DGNT# floats at power up (PWRGOOD low) and remains floated until SYSRESET goes low. On the falling edge of
SYSRESET it is sampled internally to determine the function of SA17:19. A 10K pull-up resistor should be used to
select SA17:19, or a pull-down to select the LREQ2# / LGNT2# and IOCS# functions.
PSRSTB is internally blocked when PWRGOOD is high. This allows the use of a very long time-constant RC circuit
to generate PSRSTB, without any risk of a system malfunction if PSRSTB is held low too long after the BIOS begins
executing. PSRSTB can be grounded at any time during normal system operation (PWRGOOD high) without any
effect. If PSRSTB goes low at any time while PWRGOOD is low, the RTC "VRT" bit will be cleared to alert the BIOS
that the system battery may be dead.
6.3.1. Inhibiting IPC Reset for 0V Suspend
The 4045 has an option to block reset to the IPC core following PWRGOOD rise, to support 0V suspend applications
(suspend to disk). If config register 0C bit 7 is set to a 1, the IPC core will not be reset. This config bit is reset only
when PWRGOOD and PSRSTB are both low, and will retain its value when the power is shut off, as long as the battery
voltage is maintained for the 4045. The purpose of this option is to allow a suspend to disk function without having to
reinitialize the IPC peripherals. Software should set this bit before shutting off the power when doing a suspend to
disk. It should reset the bit after resuming, so that the IPC core will be reset following a normal power off.
The IPC core includes the DMA Controllers, Interrupt Controllers, Timers, RTC, and Configuration Register 01h. The
reset inhibit does not prevent the clearing of other 4045 Configuration Registers (Indexes 08h through 0Ch) or loss of
the port 22h index value when PWRGOOD goes low. Systems that implement the 0V suspend feature must save and
restore the non-preserved Configuration Registers. If the software that decides to suspend is invoked by an SMI or
other interrupt, care must be taken not to split a port 22h/23h access, which shouldn't be happening anyway if the
system is idle and ready to suspend. Normally only the BIOS performs 22h/23h accesses and probably will inhibit
interrupts when accessing ports 22h and 23h during normal system operation.
The 4045 reset inhibit feature is intended for applications where the 4041 and CPU are both powered down during
suspend and must be reset when PWRGOOD returns to the high state. PWRGOOD must go low to put the 4045 into
its lowest current standby mode. While PWRGOOD is low, the 4045 floats SYSRESET and CPURESET, which are
pulled high by external pull-up resistors. When PWRGOOD goes high, the 4045 always keeps SYSRESET and
CPURESET high for a fixed time interval (around 250 ms if SCLK is 33.3 MHz), regardless of whether or not the 4045
internal IPC reset has been inhibited.
If the CPU and 4041 are not powered down during suspend, then other power management features such as CPU clock
control and SMI can be used to optimize system power consumption.
Revision 1.0
2/10/95
145
Preliminary
CS4041