F84045 Asiliant Technologies, F84045 Datasheet - Page 74

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

4.10. Keyboard/Mouse Controller
An internal keyboard controller state machine is provided, which directly connects to the keyboard connector. It also
includes a PS/2 style mouse port.
The mouse port or the entire keyboard controller may be disabled if special functions are required of an external 8042.
For further information, see especially Section 5.15. See also Sections 5.3.2, 5.13, and 6.13..
4.11. IDE Controller
Features:
The 4041 IDE controller has a direct local bus interface to speed up access to the IDE drive. Drive accesses are
speeded up by three means:
For further information, see Section 5.12.
4.12. CPUs Containing Writeback Caches
The CS4041 CHIPSet fully supports 486-class CPUs that contain writeback caches, including those made by Intel,
AMD, Cyrix, and other compatibles. There are several effects of a CPU write back cache, also known as "Level 1" or
L1 WB:
For further information, see Sections 1.1, 5.7, 5.8, and 5.13.1.
Revision 1.0
Memory write cycles often go only to the CPU internal WB cache and do not appear on the CPU local data bus.
This provides a performance advantage over CPU write-through caches, in which all memory writes go to the
CPU local data bus as well as to the cache (if the write is an L1 cache hit).
Data in the CPU cache may be more up-to-date than the corresponding data in DRAM. Whenever a read from
DRAM is cacheable by the CPU and is a CPU cache miss, the CPU must first write the existing L1 cache data
back out to DRAM before filling the cache line with read data from a different DRAM location. For highest
system performance, the CS4041 supports these writeback cycles by allowing them to occur as burst writes.
When an ISA Master, Local Bus Master, or DMA controlle r performs a memory read, the CPU cache may contain
the only valid copy of the data. The CPU "Hit Modified" signal, HITM# (or equivalent), alerts the CS4041
CHIPSet that this is happening. The CHIPSet then responds by allowing the CPU to write the data out to DRAM
and/or L2 cache before allowing the alternate master to complete the read operation.
Fast accesses to IDE drive data port
32 bit I/O cycles supported.
Up to 8 drives supported (up to 4 IDE addresses).
Programmable I/O read length, I/O write length, command inactive, and address setup time.
Each drive may select either of 2 programmed timing sets.
May coexist with other IDE controllers at different addresses, either local bus or ISA.
When enabled, it may disable an existing controller on the ISA bus.
Transparently supports the 3F7 register sharing with the flopp y, wherever the floppy is located.
Eliminating the overhead of an ISA bus access.
Allowing 32 bit I/O cycles to reduce CPU overhead (converted to two 16 bit IDE cycles)
Shortening the command timing to the drive
2/10/95
Subject to change without notice
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System Level Functions
Preliminary
CS4041