F84045 Asiliant Technologies, F84045 Datasheet - Page 44

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
21
22
Revision 1.0
Index
Index
21
22
0
2:1
3
6:4
7
0
1
2
3
5:4
7:6
cache config cache banks
cache test
Function
Function
Bits
Cache Controller Configuration
cache with 8-bit tag, or A0h after upgrade to dual-bank 256KB.
(Reserved. Write as 0.)
Tag width
(Reserved. Write as 0. May be used for future expansion of tag width field).
Cache size:
Single or Dual bank mode
Cache Testing Control.
Data SRAM test mode. 0 = disabled (default). 1 disables CAS for DRAM cycles within the test
Tag RAM test mode. 0 = disabled (default)
(Reserved).
SRAM and TAG RAM test window select.
(Reserved)
Code and data caching. These bits affect secondary cache line fills only. They do not affect cache
2/10/95
window.
read or write hits, which must function as normal. The L1 cache (via the KEN# signal) is not
affected.
code/data1
00
01
10
11
000
001
010
011
100
0
1
0
1
00
01
10
11
D7
D7
Description
8 bits (default)
9 bits
11 bits
(Reserved).
64K bytes (default)
128K bytes
256K bytes
512K bytes
1Mbyte
Single bank
Dual Bank
Test Window for 64K, 128K, & 256K cache: 40000h-7FFFFh;
Test Window for all cache sizes: 100000h-1FFFFFh
Code and data cache.
Code only
Data only
(Reserved)
cache size2
code/data0
D6
D6
Subject to change without notice
cache size1
Default = 00. Typical setting = 00h for normal operation.
D5
D5
-
for 512K cache: 20000:9FFFF.
cache size0
43
Default = 00. Typical setting = 40h for single-bank 128KB
D4
D4
-
test window
D3
D3
-
tag width 1
D2
D2
-
tag width 0
tag test
Configuration Registers
Preliminary
D1
D1
tag wr time
SRAM test
D0
D0
CS4041