F84045 Asiliant Technologies, F84045 Datasheet - Page 154

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

One of the 8237s is used for 8 bit DMA, with its address lines mapped directly onto the system address bus. The other
DMA controller is adapted to make it perform 16 bit DMA. This is done by shifting the address lines by one position,
and forcing A0 to a 0. Software must shift the address by 1 bit before loading the DMA controller's registers. Each
time the address in the DMA controller increments, it effectively increments the resulting system address by 2. The
lower 4 address lines on an 8237 are used to select the register when programming the chip. Because they are shifted
by one position in the 16 bit controller, the registers only show up on every other IO port. Because of this arrangement,
there are several restrictions on DMA in all PC/AT compatible system:
Each DMA controller has a HOLD output and an HLDA input, plus 4 DREQ inputs and 4 DACK# outputs (the DREQs
and DACKs have programmable polarity, but the AT standard is active high for DREQ (for unknown reasons, although
it's useful for testing), and active low for DACK. The 16 bit channel’s HOLD and HLDA signals become the external
HOLD and HLDA signals after processing by the arbitration logic. The 8 bit controller’s HOLD and HLDA are
connected to the 16 bit controller’s DREQ0 and DACK0#. This channel, which would have been channel 4 otherwise,
is put in “cascade mode.” This means that the 8 bit controller goes through the 16 bit controller to get the bus, adding
some overhead to its arbitration.
Cascade mode, which basically converts DREQ/DACK pair into a HOLD/HLDA protocol, is also used by ISA bus
masters to get the bus. A DMA channel in this mode will request the bus in response to a DREQ, and take DACK#
low when it gets the bus, but will not drive the address or control signals for the DMA cycle, expecting something else
to do it (the ISA master or a external DMA controller). The DACK# stays active until the DREQ goes low.
The upper DMA addresses (A16:23 for the 8 bit controller and A17:23 for the 16 bit controller) are provided by a small
dual port RAM, also known as the DMA Page Register array, which was implemented with a 74LS612 in the IBM
PC/AT. One port is IO mapped and used to write and read the RAM. The other port has a separate set of internal
address lines and outputs. The address lines are controlled by a complex combination of the DACK# signals which
saved logic on the original PC/AT, but made the IO port ordering confusing. Only 8 of the 16 locations are used for
DMA (one of which is output for REFRESH cycles). D7:0 map to A23:16 respectively, but bit D0 (A16) not used for
16 bit channels. The page register bits are not shifted.
DMA cycles are done by transferring the data directly from the IO device to the memory device. IOR# and MEMW#
are activated together for memory writes, and MEMR# and IOW# are activated for memory reads. The data is not held
in any intervening register.
For memory writes, IOR# goes low one DMA clock before the MEMW# since “extended write” mode is always used.
This is necessary since the data must be stable from the IO device before CAS falls on the DRAMs, which is timed
from the beginning of MEMW#. For memory reads, MEMR# is delayed by internal logic outside the 8237 to match
the IOW# command. IO devices should latch the data on the rising edge of IOW# since it won’t be there anywhere
near the beginning. The MEMR# delay is presumably there to allow enough address setup time to the DRAM
controller. RAS# is generated with MEMR# going low. The MEMR# delay is programmable in the IPC through
Index 01h.
SIPC LOUT acts as a strobe to latch DMA address bits A10:16 into the 4041 from the XD bus. These address bits are
not connected to the SIPC (to optimize the pin count). The SIPC drives SA0:7 directly during DMA, along with A8:9
(which are also used by the SIPC as inputs during I/O reads and writes to SIPC registers). Address generation during
DMA is summarized below.
Revision 1.0
Channels 0, 1, 2, and 3 are always used for 8 bit DMA.
Channels 5, 6, and 7 are always used for 16 bit DMA.
8 bit DMA must be within a 64KB memory range (only the 16 bit address increments) until software updates the
16 bit DMA must be within a 128KB memory range (the address is shifted by 1 bit) until software updates the
corresponding page register.
corresponding page register.
2/10/95
Subject to change without notice
153
Preliminary
Functional Description
CS4041