F84045 Asiliant Technologies, F84045 Datasheet - Page 40

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
14-17
14
15
16
17
18
Revision 1.0
Index
18
Index
14
15
16
17
7:0
0
1
2
3
4
5
6
7
vid shad, etc. wprotmode
Function
start add 0
start add 1
start add 2
start add 3
Function
Bits
DRAM block 0-3 Starting Address
addressed block in the system, 01h for a block that starts at 1MB, and so on. Largest blocks should be
programmed for lowest starting addresses.
DRAM block 0 Starting address
DRAM block 1 Starting address
DRAM block 2 Startin g address
DRAM block 3 Starting address
A27-A20 of starting address
Video area shadow and local bus control.
A0000-AFFFF Shadow enable.
B0000-BFFFF Shadow enab le.
Shadow RAM L1 cache disable
Shadow RAM L2 cache disable
Local Bus time-out
LDEV# Sample point.
Shadow RAM WB / WT#
Write Protect Method.
2/10/95
0
1
0
1
0
1
Do not set this bit to ‘1’ unless bit 3 is also ‘1’. (This restriction does not apply to Index 18h
0
1
0
1
0
1
0
1
0
1
If bit 7 is ‘1’, bit 6 typically should also be set to ‘1’ when using shadow RAM for SMM
D7
A27
A27
A27
A27
D7
Description
Access goes to the ISA bus.
Access goes to local DRAM.
Access goes to the ISA bus.
Access goes to local DRAM.
Shadow RAM is cacheable in L1
L1 Cache disabled for shadow RAM (A0000:FFFFF DRAM).
Shadow RAM is cacheable in L2.
L2 Cache disabled for shadow RAM (A0000:FFFFF DRAM).
No time out (default)
Time out enabled
end of first T2.
end of second T2. This delays the start of all ISA bus accesses.
Shadow RAM may be write back in L1.
Shadow RAM is write through in L1 (may be WB in L2)
Write protected DRAM is not put in the 486 cache.
Write protected DRAM is placed in the 486 cache, and EADS# is generated on all
eads lbm
D6
A26
A26
A26
A26
bit 7 or Index 94h bit 3.)
writes.
with a writeback CPU, unless SMM is non-cacheable in L1. (see section
5.9.5.1.)
D6
Subject to change without notice
local sample local timeout sh ram L2 dis sh ram L1 dis
D5
A25
A25
A25
A25
D5
39
D4
A24
A24
A24
A24
D4
Default = 00. Typical setting = 00h for the lowest
Default = 00. Typical setting = 80h.
A23
A23
A23
A23
D3
D3
A22
A22
A22
A22
D2
D2
shadow B0
Configuration Registers
Preliminary
A21
A21
A21
A21
D1
D1
shadow A0
A20
A20
A20
A20
D0
D0
CS4041