F84045 Asiliant Technologies, F84045 Datasheet - Page 116

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.10.8. Automatic DRAM Sizing & Setup
The BIOS normally should auto-size the DRAM and support any possible DRAM configuration. It should not require
any DRAM to be installed in block 0 or any other particular block. The BIOS should assume that there are four
double-bank 72-pin SIMM sockets and that the user may install any valid DRAM type into any socket in any
combination.
Each block can be checked individually, leaving other blocks disabled during the test. The block to be tested can be
programmed as 16M deep, non-interleaved, single-bank. The various possible physical DRAM sizes will then function
as described below:
To test for a second bank in a block, program the block for the correct DRAM size as previously detected, and set the
block for two banks. If alternate DRAM pages are missing, only one bank is installed in the block. The page size is
2KB (800h) for 256K deep DRAM, or 4KB (1000h) for all other DRAM sizes.
After sizing each block, enable interleaving between banks where possible. Two banks may be interleaved if the are
single-bank blocks of the same size, and one is even (RAS0# or RAS2#) while the other is odd (RAS1# or RAS3#).
Finally, program the block starting addresses so that the largest blocks map lowest in the address space. If two banks
are interleaved, they should map lower in the address space than a single bank of the same DRAM type. Interleaving
doubles the effective block size for a given DRAM size. For example, a block containing two 4M deep DRAM banks
(or two single-bank 4M deep blocks interleaved together) should map lower than a single 4M deep DRAM bank, but
higher than a single 16M deep DRAM bank.
5.11. ISA Bus
5.11.1. CPU or VL Master Accesses to the ISA Bus
Bus cycles which do not get claimed by a local slave or the DRAM controller go to the ISA bus by default. Secondary
cache has the first opportunity to claim a cycle. Next comes local DRAM, then VL slaves (via LDEV#), and finally
ROM connected to ROMCS#. If the cycle is not claimed by any of these, it goes to the ISA bus. I/O cycles not
claimed by LDEV# go to the ISA bus, except that I/O reads from on-chip or XD-bus peripherals will have the data
busses steered as needed, blocking SD-bus data.
The ISA bus runs off of a clock which is derived from CLKIN. It should normally be set at about 8MHz, but may be
set faster if all of the peripherals can handle the faster cycles. See the Clock section above for programming the ISA
bus clock rate.
As noted in the Pin Descriptions and Figure 1, the MA2:9 lines are used for XD8:15 as well as the DRAM address,
depending on whether the cycle is an ISA bus cycle or DRAM access.
Revision 1.0
256K deep (1MB total)
26 are ignored, causing pages to repeat at 2MB intervals (0020 0000h).
1M deep (4MB total)
0000h).
4M deep (16MB total)
causing pages to repeat at 32MB intervals (0200 0000h).
16M deep (64MB total)
2/10/95
no missing pages. A22-26 are ignored, causing pages to repeat at 4MB intervals (0040
page size will be 2KB (800h). Leave A11 always zero (alternate pages missing). A21-
no missing or repeated pages over a full 64MB range (0400 0000h).
page size is 4KB (1000h). Leave A23 and A24 always zero. A25-26 are ignored,
Subject to change without notice
115
Preliminary
Functional Description
CS4041