F84045 Asiliant Technologies, F84045 Datasheet - Page 41

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
19
1A
1B
Note: Memory read or write cycles in the range FFFx xxxxh (top 1MB) always go to ROM (ROMCS# generated, ISA
19,1A 7
1B
1C
Revision 1.0
Index
Index
cycle timing) regardless of the value in Index 1Bh, and WPROT# (Index 3Dh) remains high.
1A
1B
1C
19
Bit assignments for registers 19, 1A, and 1B:
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
shad SMM
shadow wr
shadow rd
Function
ROMCS
Function
Bits
DRAM shadow read enable.
BIOS are both shadowed. If a bit in the list below is 0, reads in the corresponding address range come
from the ISA bus. If a bit is a 1, reads in that range come from local DRAM. See also Index 1Dh.
DRAM shadow write enable.
RAM. If a bit in the list below is 0, writes to the corresponding address range go to the ISA bus. If a
bit is a 1, writes to that range go to the local DRAM. See also Index 1Dh.
ROMCS enable.
firmware (Exxxxh) both in ROM, or 63h for system BIOS (Fxxxxh) and extension firmware (Exxxxh)
and video BIOS (C0xxxh-C7xxxh) all in one ROM. If a bit is 1, ISA bus reads from that location
activate ROMCS#. If a bit is a 0, ROMCS# is not activated. ROMCS# will not be activated if an
access is directed to local DRAM, i.e., indexes 19h and 1Ah have precedence over 1Bh. Bit 7
determines whether to activate ROMCS# on writes.
C0000-C3FFF.
C4000-C7FFF.
C8000-CBFFF.
CC000-CFFFF.
D0000-DFFFF.
E0000-EFFFF.
F0000-FFFFF.
(Reserved)
Activate ROMCS on writes also. default=0.
SMM shadow enable.
This register is used instead of registers 19 and 1A bits 6:4 while in SMM mode, allowing DRAM to
be enabled only during SMM mode. If a bit is 0, reads or writes from that location come from the ISA
bus. If a bit is a 1, reads or writes from that location come from local DRAM. See also Index 1Dh.
D0000-DFFFF read enable.
E0000-EFFFF read enable.
F0000-FFFFF read enable.
(Reserved)
D0000-DFFFF write enable.
E0000-EFFFF write enable.
F0000-FFFFF write enable.
(Reserved)
2/10/95
Rom WR
0
1
D7
D7
-
-
-
Description
do not activate on writes.
activate ROMCS# on ISA writes to the addresses selected by bits 0-6.
sm w F0000 sm w E0000 sm w D0000
Rom F0000 Rom E0000 Rom D0000 Rom CC000 Rom C8000 Rom C4000 Rom C0000
WR F0000
RD F0000
D6
D6
Default = 60h. Typical setting = 60h for system BIOS (Fxxxxh) and extension
Subject to change without notice
Default = 00. Typical setting = 77h.
WR E0000
RD E0000
D5
D5
Default = 00. Typical setting = 00h for write-protected shadow
Default = 00. Typical setting = 43h if system BIOS and video
WR D0000
RD D0000
40
D4
D4
WR CC000
RD CC000
D3
D3
-
sm r F0000
WR C8000
RD C8000
D2
D2
WR C4000
sm r E0000
RD C4000
Configuration Registers
Preliminary
D1
D1
sm r D0000
WR C0000
RD C0000
D0
D0
CS4041