RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 10

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

1.0 RS8234 Product Overview
1.1 Introduction
1-2
following mechanisms. First, each peer maintains separate control and status
queues. Then, each VCC in a peer group may be limited to a specific maximum
receive buffer utilization, further controlling congestion. EPD is supported for
VCCs that exceed their resource allotments. On transmit, peers are assigned fixed
or round robin priority to ensure predictable servicing. The host can implement a
congestion notification algorithm for ABR with a simple one-word write to an
SAR control register. The SAR will reduce the Explicit Rate (ER) field or set the
Congestion Indication (CI) bit in Turnaround (Resource Management (RM) cells,
based on user configuration.
This memory is controlled by the SAR through the local bus interface, which
arbitrates access to the bus between the various coprocessors. Although these
coprocessors run off the same system clock, they operate asynchronously from
each other. Communication between the coprocessors takes place through on-chip
FIFO buffers or through queues in SAR-shared memory (that is, memory local to
the SAR and accessible both to the SAR and the host).
performance PCI and UTOPIA ports for glueless interface to a variety of system
components with full line rate throughput and low bus occupancy.
illustrates these functional blocks.
The RS8234 host interface provides for control of host congestion through the
The RS8234 consists of five separate coprocessors:
• Incoming DMA,
• Outgoing DMA,
• Reassembly,
• Segmentation, and
• xBR Traffic Manager
Each coprocessor maintains state information in shared, off-chip memory.
The RS8234’s on-chip coprocessor blocks are surrounded by high
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
Figure 1-1
RS8234