RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 42

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.2 High Performance Host Architecture with Buffer Isolation
2.2.5 Write-Only Control/Status
Figure 2-8. Write-Only Control and Status Architecture
2.2.6 Scatter/Gather DMA
2-10
Host
Figure 2-8
manages the RS8234 ATM terminal using write-only control and status queues.
This architecture minimizes PCI bus utilization by eliminating reads from control
activities. PCI writes utilize the bus much more efficiently than PCI reads. During
a PCI write, the Bus Master can post the write data to an internal FIFO in the
slave, terminate the transaction, and immediately release the bus. On the other
hand, during PCI reads, the Bus Master retrieves the data from the slave while
holding the bus. Since the data retrieval takes some time, reads increase the PCI
bus utilization time for each transaction. The RS8234 eliminates read operations
except for burst reads to gather segmentation data.
The RS8234’s Direct Memory Access (DMA) coprocessor works in close
conjunction with the segmentation and reassembly coprocessors to gain access to
the PCI bus, transfer the requested data, and notify the segmentation or
reassembly coprocessor that the transfer is complete. The DMA coprocessor
transfers all data using the read and write burst buffers in the PCI Bus Interface.
accesses for data, or 1- to 4-word accesses for control and status messages.
to the segmentation coprocessor using a gather DMA method. For incoming
messages, the DMA coprocessor moves data from the reassembly coprocessor to
host memory using a scatter DMA method.
data that is not aligned on word boundaries. It will also selectively transfer data to
comply with either a big endian or little endian host data structure.
Write-only architecture reduces PCI utilization dramatically,
In general, two types of transactions are processed: 12- or 14-word burst
For outgoing messages, the DMA coprocessor moves data from host memory
The DMA coprocessor is capable of handling transfers from the PCI bus with
Mindspeed Technologies
as reads take many more clock cycles.
illustrates the RS8234’s write-only PCI control architecture. The host
SEG Data (Read Multiples)
RSM Data (Writes)
Control
Status
PCI
ATM ServiceSAR Plus with xBR Traffic Management
™
RS8234
28234-DSH-001-B
RS8234
100074_009