RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 354

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

15.0 Electrical and Mechanical Specifications
15.1 Timing
15.1.6 Local Processor Interface Timing
Timing for the local processor interface can be broken into two sections. The first is the synchronous to
SYSCLK interface of processor control signals to and from the RS8234. The second is the interface to the SAR
shared memory and the RS8234 control and status registers, which involves both SRAM and transceiver, as well
as buffer timing parameters that are not specified and are left up to the system designer.
of the RS8234 (PRDY*). The output loading of these signals is 35 pF for the timing given in
Memory Interface Timing is given in
Table 15-9. Synchronous Processor Interface Timing
15-14
NOTE(S):
(1)
(2)
All of the synchronous interface signals are inputs to the RS8234 except for SYSCLK and the ready output
Symbol
See
See
t
t
t
ov
ih
is
Figure 15-11
Figure 15-12
PCS* Input Setup
PAS* Input Setup
PBLAST* Input Setup
PWAIT* Input Setup
PADDR[1,0] Input Setup
PBSEL[1,0] Input Setup
PBE[3:0]* Input Setup
PWNR Input Setup
PCS* Input Hold
PAS* Input Hold
PBLAST* Input Hold
PWAIT* Input Hold
PADDR[1,0] Input Hold
PBSEL[1,0] Input Hold
PBE[3:0]* Input Hold
PWNR Input Hold
PRDY* Output Valid Delay
for waveforms and definitions.
for waveforms and definitions. The outputs are measured with a load of 35 pF.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Parameter
Table
(1)
(1)
(1)
(1)
(1)
Mindspeed Technologies
(2)
15-10.
Synchronous Outputs
Synchronous Inputs
ATM ServiceSAR Plus with xBR Traffic Management
™
Min
10
10
10
10
10
8
8
8
0
0
0
0
0
0
0
0
5
Max
15
28234-DSH-001-B
Table
15-9.
RS8234
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns